公开(公告)号：US20240264950A1

公开(公告)日：2024-08-08

申请号：US18163446

申请日：2023-02-02

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Engin Ipek ,  Goran Goran ,  Hamza Omar ,  Bohuslav Rychlik ,  Jeffrey Gemar ,  Matthew Severson ,  Andrew Edmund Turner

IPC: G06F12/126 ,  G06F12/0888

CPC classification number: G06F12/126 ,  G06F12/0888 ,  G06F2212/502

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

公开(公告)号：US20220019534A1

公开(公告)日：2022-01-20

申请号：US16931490

申请日：2020-07-17

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik ,  George Patsilaras

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F12/10 ,  G06F12/0891

Abstract: Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.

公开(公告)号：US09582329B2

公开(公告)日：2017-02-28

申请号：US14623554

申请日：2015-02-17

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  George Patsilaras

IPC: G06F9/54 ,  G06F9/50 ,  G06F12/08

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F9/5088 ,  G06F12/0811 ,  G06F12/084 ,  G06F2209/502 ,  G06F2209/505 ,  G06F2212/1024 ,  G06F2212/502

Abstract: Aspects include computing devices, systems, and methods for implementing scheduling an execution process to an execution processor cluster to take advantage of reduced latency with a victim cache. The computing device may determine a first processor cluster with a first remote shared cache memory having an available shared cache memory space. To properly schedule the execution process, the computing device may determine a second processor cluster with a lower latency to the first remote shared cache memory than an execution processor cluster scheduled with the execution process. The second processor cluster may be scheduled the execution process, thus becoming the execution processor cluster, based on a size of the available shared cache memory space and the latency of the second processor cluster to the first remote shared cache memory. The available shared cache memory space may be used as the victim cache for the execution process.

Abstract translation: 方面包括用于实现将执行过程调度到执行处理器集群以利用受害缓存的减少的延迟的计算设备，系统和方法。 计算设备可以使用具有可用共享高速缓冲存储器空间的第一远程共享高速缓冲存储器来确定第一处理器群集。 为了适当地安排执行过程，计算设备可以确定具有比执行处理调度的执行处理器群具有比第一远程共享高速缓冲存储器更低延迟的第二处理器群集。 可以基于可用的共享高速缓冲存储器空间的大小和第二处理器群集到第一远程共享高速缓冲存储器的等待时间来调度第二处理器群集，从而成为执行处理器群集。 可用的共享缓存存储器空间可以用作执行过程的受害缓存。

公开(公告)号：US12182036B2

公开(公告)日：2024-12-31

申请号：US18163446

申请日：2023-02-02

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Engin Ipek ,  Goran Goran ,  Hamza Omar ,  Bohuslav Rychlik ,  Jeffrey Gemar ,  Matthew Severson ,  Andrew Edmund Turner

IPC: G06F12/126 ,  G06F12/0888

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

公开(公告)号：US11681624B2

公开(公告)日：2023-06-20

申请号：US16931490

申请日：2020-07-17

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik ,  George Patsilaras

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/10

CPC classification number: G06F12/0815 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/657

Abstract: Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.

公开(公告)号：US09665489B2

公开(公告)日：2017-05-30

申请号：US14619628

申请日：2015-02-11

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  Bohuslav Rychlik ,  George Patsilaras ,  Andrew Edmund Turner ,  Anwar Quinones Rohillah

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F12/084 ,  G06F12/0851 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing selecting an available shared cache memory as a victim cache. The computing device may identify a remote shared cache memory with available shared cache memory space for use as the victim cache. To select the appropriate available shared cache memory, the computing device may retrieve data for the identified remote shared cache memory or a processor cluster associated with the identified remote shared cache memory relating to a metric, such as performance speed, efficiency, or effective victim cache size. Using the retrieved data, the computing device may determine the identified remote shared cache memory to use as the victim cache and select the determined remote shared cache memory to use as the victim cache.

公开(公告)号：US20160232091A1

公开(公告)日：2016-08-11

申请号：US14619628

申请日：2015-02-11

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  Bohuslav Rychlik ,  George Patsilaras ,  Andrew Edmund Turner ,  Anwar Quinones Rohillah

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0851 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing selecting an available shared cache memory as a victim cache. The computing device may identify a remote shared cache memory with available shared cache memory space for use as the victim cache. To select the appropriate available shared cache memory, the computing device may retrieve data for the identified remote shared cache memory or a processor cluster associated with the identified remote shared cache memory relating to a metric, such as performance speed, efficiency, or effective victim cache size. Using the retrieved data, the computing device may determine the identified remote shared cache memory to use as the victim cache and select the determined remote shared cache memory to use as the victim cache.

Abstract translation: 方面包括用于实现选择可用的共享高速缓冲存储器作为受害者高速缓存的计算设备，系统和方法。 计算设备可以使用可用的共享高速缓冲存储器空间来识别远程共享高速缓冲存储器，以用作受害者高速缓存。 为了选择适当的可用共享高速缓冲存储器，计算设备可以检索与所标识的远程共享高速缓冲存储器相关联的识别的远程共享高速缓冲存储器的数据或与所标识的远程共享高速缓冲存储器有关的诸如性能速度， 尺寸。 使用所检索的数据，计算设备可以确定所识别的远程共享高速缓冲存储器以用作受害者高速缓存，并选择确定的远程共享高速缓冲存储器以用作受害者高速缓存。

公开(公告)号：US20240422336A1

公开(公告)日：2024-12-19

申请号：US18337116

申请日：2023-06-19

Applicant: QUALCOMM Incorporated

Inventor： Younghoon Kim ,  George Patsilaras ,  Shengqi Yang ,  Tomoyuki Naito ,  Giwon Kim ,  Vladan Andrijanic ,  Vipul Gandhi ,  Jaemoon Kim ,  Aravind Bhaskara ,  Mohit Hari Bhave ,  Rohit Thulasiram

IPC: H04N19/423 ,  H04N19/105 ,  H04N19/159 ,  H04N19/172

Abstract: A method includes determining a picture type of a current picture, determining, based on the picture type of the current picture, whether to write the current picture in a dedicated chip memory or whether to write the current picture a non-dedicated system memory, and writing the current picture in the dedicated chip memory or the non-dedicated system memory based on the determining of whether to write the current picture in the dedicated chip memory or whether to write the current picture in the non-dedicated system memory.

公开(公告)号：US20230359373A1

公开(公告)日：2023-11-09

申请号：US17661810

申请日：2022-05-03

Applicant: QUALCOMM Incorporated

Inventor： Engin Ipek ,  Hamza Omar ,  Bohuslav Rychlik ,  Saumya Ranjan Kuanr ,  Behnam Dashtipour ,  Michael Hawjing Lo ,  Jeffrey Gemar ,  Matthew Severson ,  George Patsilaras ,  Andrew Edmund Turner

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0673

Abstract: Selective refresh techniques for memory devices are disclosed. In one aspect, a memory device that is used with an application that has frequent repeated read or write commands to certain memory segments may be able to set a flag or similar indication that exempts these certain memory segments from being actively refreshed. By exempting these memory segments from being actively refreshed, these memory segments are continuously available, thereby improving performance. Likewise, because these memory segments are so frequently the subject of a read or write command, these memory segments are indirectly refreshed through the execution of the read or write command.

公开(公告)号：US20230029696A1

公开(公告)日：2023-02-02

申请号：US17390274

申请日：2021-07-30

Applicant: QUALCOMM Incorporated

Inventor： Girish Bhat ,  Subbarao Palacharla ,  Jeffrey Shabel ,  Isaac Berk ,  Kedar Bhole ,  Vipul Gandhi ,  George Patsilaras ,  Sparsh Singhai

IPC: G06F12/084 ,  G06F1/3212

Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.