公开(公告)号：US10169246B2

公开(公告)日：2019-01-01

申请号：US15592611

申请日：2017-05-11

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1036

Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.

公开(公告)号：US20180329830A1

公开(公告)日：2018-11-15

申请号：US15592611

申请日：2017-05-11

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/1045 ,  G06F3/06

CPC classification number: G06F12/1036 ,  G06F3/06 ,  G06F3/0608 ,  G06F3/0661 ,  G06F3/0685 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/60

Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.

公开(公告)号：US20180217930A1

公开(公告)日：2018-08-02

申请号：US15420667

申请日：2017-01-31

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/0808 ,  G06F12/128

CPC classification number: G06F12/0808 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/128 ,  G06F2212/401 ,  G06F2212/621 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: Aspects disclosed involve reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur. A processor-based system is provided that includes a cache memory and a compression memory system. When a cache entry is evicted from the cache memory, cache data and a virtual address associated with the evicted cache entry are provided to the compression memory system. The compression memory system reads metadata associated with the virtual address of the evicted cache entry to determine the physical address in the compression memory system mapped to the evicted cache entry. If the metadata is not available, the compression memory system stores the evicted cache data at a new, available physical address in the compression memory system without waiting for the metadata. Thus, buffering of the evicted cache data to avoid or reduce stalling write operations is not necessary.

公开(公告)号：US10198362B2

公开(公告)日：2019-02-05

申请号：US15426473

申请日：2017-02-07

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/08 ,  G06F12/128 ,  G06F12/02 ,  G06F12/0875 ,  G06F12/0897

Abstract: Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.

公开(公告)号：US10061698B2

公开(公告)日：2018-08-28

申请号：US15420667

申请日：2017-01-31

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/128

Abstract: Aspects disclosed involve reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur. A processor-based system is provided that includes a cache memory and a compression memory system. When a cache entry is evicted from the cache memory, cache data and a virtual address associated with the evicted cache entry are provided to the compression memory system. The compression memory system reads metadata associated with the virtual address of the evicted cache entry to determine the physical address in the compression memory system mapped to the evicted cache entry. If the metadata is not available, the compression memory system stores the evicted cache data at a new, available physical address in the compression memory system without waiting for the metadata. Thus, buffering of the evicted cache data to avoid or reduce stalling write operations is not necessary.

公开(公告)号：US20180225224A1

公开(公告)日：2018-08-09

申请号：US15426473

申请日：2017-02-07

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/128 ,  G06F12/02

CPC classification number: G06F12/128 ,  G06F12/023 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.

公开(公告)号：US20180173623A1

公开(公告)日：2018-06-21

申请号：US15385991

申请日：2016-12-21

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/0804 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Aspects disclosed involve reducing or avoiding buffering evicted cache data from an uncompressed cache memory in a compressed memory system to avoid stalling write operations. Metadata is included in cache entries in the uncompressed cache memory, which is used for mapping cache entries to physical addresses in the compressed memory system. When a cache entry is evicted, the compressed memory system uses the metadata associated with the evicted cache data to determine the physical address in the compressed system memory for storing the evicted cache data. In this manner, the compressed memory system does not have to incur the latency associated with reading the metadata for the evicted cache entry from another memory structure that may otherwise require buffering the evicted cache data until the metadata becomes available, to write the evicted cache data to the compressed system memory to avoid stalling write operations.