Device and method for computing a channel estimate
    1.
    发明授权
    Device and method for computing a channel estimate 有权
    用于计算信道估计的装置和方法

    公开(公告)号:US09130786B2

    公开(公告)日:2015-09-08

    申请号:US13842663

    申请日:2013-03-15

    CPC classification number: H04L25/0212 H04B1/70752 H04B1/7093 H04B2201/70707

    Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

    Abstract translation: 一种装置包括选择逻辑,其被配置为选择存储在第一组寄存器中的第一组采样的第一子集。 第一子集包括存储在第一组寄存器的第一寄存器中的第一样本,并且还包括存储在第一组寄存器的第二寄存器上的第二样本。 该装置还包括移位逻辑,配置成移位存储在第二组寄存器中的第二组采样。 该装置还包括信道估计器,其被配置为基于第一子集生成与信道估计相关联的第一值,并且还基于所移位的第二组样本的第二子集。

    DEVICE AND METHOD FOR COMPUTING A CHANNEL ESTIMATE
    3.
    发明申请
    DEVICE AND METHOD FOR COMPUTING A CHANNEL ESTIMATE 有权
    用于计算通道估计的装置和方法

    公开(公告)号:US20140270017A1

    公开(公告)日:2014-09-18

    申请号:US13842663

    申请日:2013-03-15

    CPC classification number: H04L25/0212 H04B1/70752 H04B1/7093 H04B2201/70707

    Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

    Abstract translation: 一种装置包括选择逻辑,其被配置为选择存储在第一组寄存器中的第一组采样的第一子集。 第一子集包括存储在第一组寄存器的第一寄存器中的第一样本,并且还包括存储在第一组寄存器的第二寄存器上的第二样本。 该装置还包括移位逻辑,配置成移位存储在第二组寄存器中的第二组采样。 该装置还包括信道估计器,其被配置为基于第一子集生成与信道估计相关联的第一值,并且还基于所移位的第二组样本的第二子集。

    Vector indirect element vertical addressing mode with horizontal permute

    公开(公告)号:US09639503B2

    公开(公告)日:2017-05-02

    申请号:US13834785

    申请日:2013-03-15

    Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

    Vector indirect element vertical addressing mode with horizontal permute

    公开(公告)号:US09606960B2

    公开(公告)日:2017-03-28

    申请号:US13834785

    申请日:2013-03-15

    Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

    Arbitrary size table lookup and permutes with crossbar

    公开(公告)号:US09639356B2

    公开(公告)日:2017-05-02

    申请号:US13842751

    申请日:2013-03-15

    CPC classification number: G06F9/30032 G06F9/30036 G06F9/30072

    Abstract: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.

    CYCLE SLICED VECTORS AND SLOT EXECUTION ON A SHARED DATAPATH
    7.
    发明申请
    CYCLE SLICED VECTORS AND SLOT EXECUTION ON A SHARED DATAPATH 审中-公开
    循环切片向量和分段执行在共享数据

    公开(公告)号:US20140281368A1

    公开(公告)日:2014-09-18

    申请号:US13829503

    申请日:2013-03-14

    CPC classification number: G06F9/3853

    Abstract: An example method for executing multiple instructions in one or more slots includes receiving a packet including multiple instructions and executing the multiple instructions in one or more slots in a time shared manner. Each slot is associated with an execution data path or a memory data path. An example method for executing at least one instruction in a plurality of phases includes receiving a packet including an instruction, splitting the instruction into a plurality of phases, and executing the instruction in the plurality of phases.

    Abstract translation: 用于在一个或多个时隙中执行多个指令的示例性方法包括接收包括多个指令的分组,并以时间共享的方式在一个或多个时隙中执行多个指令。 每个时隙与执行数据路径或存储器数据路径相关联。 用于执行多个阶段中的至少一个指令的示例性方法包括:接收包括指令的分组,将指令分解成多个阶段,以及执行多个阶段中的指令。

    Selective coupling of an address line to an element bank of a vector register file
    8.
    发明授权
    Selective coupling of an address line to an element bank of a vector register file 有权
    选择性地将地址线耦合到向量寄存器文件的元素库

    公开(公告)号:US09268571B2

    公开(公告)日:2016-02-23

    申请号:US13654730

    申请日:2012-10-18

    Abstract: A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.

    Abstract translation: 一种方法包括根据选择模式将多个地址线的第一地址线和多个地址线的第二地址线选择性地耦合到向量寄存器堆的多个元素组的第一元素组。 该方法还包括通过单个读取端口访问由第一地址线选择性寻址的存储在第一元素库内的数据。

    ARBITRARY SIZE TABLE LOOKUP AND PERMUTES WITH CROSSBAR
    9.
    发明申请
    ARBITRARY SIZE TABLE LOOKUP AND PERMUTES WITH CROSSBAR 有权
    ARBITRARY SIZE TABLE LOOKUP和PERMUTES WITH CROSSBAR

    公开(公告)号:US20140281421A1

    公开(公告)日:2014-09-18

    申请号:US13842751

    申请日:2013-03-15

    CPC classification number: G06F9/30032 G06F9/30036 G06F9/30072

    Abstract: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.

    Abstract translation: 更新输出数据向量的示例方法包括识别包括元素数据值的数据值向量。 该方法还包括识别包括一组元素的地址值向量。 该方法还包括将条件运算符应用于地址值向量中的该组元素的每个元素。 该方法还包括数据值向量中的每个元素数据值,基于应用条件运算符来确定是否更新输出数据向量。

    VECTOR INDIRECT ELEMENT VERTICAL ADDRESSING MODE WITH HORIZONTAL PERMUTE
    10.
    发明申请
    VECTOR INDIRECT ELEMENT VERTICAL ADDRESSING MODE WITH HORIZONTAL PERMUTE 有权
    矢量间接元件垂直寻址方式

    公开(公告)号:US20140281372A1

    公开(公告)日:2014-09-18

    申请号:US13834785

    申请日:2013-03-15

    Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

    Abstract translation: 将一个或多个元素数据值放置在输出向量中的示例性方法包括识别包括多个元素的垂直置换控制向量,所述多个元素中的每个元素包括寄存器地址。 该方法还包括对于多个元件的每个元件,从垂直置换控制向量读取寄存器地址。 该方法还包括基于寄存器地址检索多个元素数据值。 该方法还包括识别包括对应于输出向量的一组地址的水平置换控制向量。 该方法还包括基于水平置换控制向量中的地址集合将至少一些所检索到的多个元素数据值的元素数据值放入输出向量中。

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