公开(公告)号：US20140270017A1

公开(公告)日：2014-09-18

申请号：US13842663

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Deepak Mathew ,  Ajay Anant Ingle ,  Mao Zeng ,  Marc M. Hoffman

IPC: H04L25/02

CPC classification number: H04L25/0212 ,  H04B1/70752 ,  H04B1/7093 ,  H04B2201/70707

Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

Abstract translation: 一种装置包括选择逻辑，其被配置为选择存储在第一组寄存器中的第一组采样的第一子集。 第一子集包括存储在第一组寄存器的第一寄存器中的第一样本，并且还包括存储在第一组寄存器的第二寄存器上的第二样本。 该装置还包括移位逻辑，配置成移位存储在第二组寄存器中的第二组采样。 该装置还包括信道估计器，其被配置为基于第一子集生成与信道估计相关联的第一值，并且还基于所移位的第二组样本的第二子集。

公开(公告)号：US20140258680A1

公开(公告)日：2014-09-11

申请号：US13785017

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Ajay Anant Ingle ,  Lucian Codrescu ,  Suresh K. Venkumahanti ,  Jose Fridman

IPC: G06F9/38

CPC classification number: G06F9/3881 ,  G06F9/3802

Abstract: Techniques are addressed for parallel dispatch of coprocessor and thread instructions to a coprocessor coupled to a threaded processor. A first packet of threaded processor instructions is accessed from an instruction fetch queue (IFQ) and a second packet of coprocessor instructions is accessed from the IFQ. The IFQ includes a plurality of thread queues that are each configured to store instructions associated with a specific thread of instructions. A dispatch circuit is configured to select the first packet of thread instructions from the IFQ and the second packet of coprocessor instructions from the IFQ and send the first packet to a threaded processor and the second packet to the coprocessor in parallel. A data port is configured to share data between the coprocessor and a register file in the threaded processor. Data port operations are accomplished without affecting operations on any thread executing on the threaded processor.

Abstract translation: 解决了将协处理器和线程指令并行调度到耦合到线程处理器的协处理器的技术。 从指令队列（IFQ）访问第一个线程处理器指令包，并从IFQ访问第二个协处理器指令包。 IFQ包括多个线程队列，每个线程队列被配置为存储与特定指令线程相关联的指令。 调度电路被配置为从IFQ和来自IFQ的协处理器指令的第二分组选择线程指令的第一分组，并且将第一分组并行地发送到线程处理器，并将第二分组发送到协处理器。 数据端口被配置为在协处理器和线程处理器中的寄存器文件之间共享数据。 完成数据端口操作，而不影响在线程处理器上执行的任何线程的操作。

公开(公告)号：US09639356B2

公开(公告)日：2017-05-02

申请号：US13842751

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Marc M. Hoffman ,  Ajay Anant Ingle ,  Jose Fridman

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30072

Abstract: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.

公开(公告)号：US20140281368A1

公开(公告)日：2014-09-18

申请号：US13829503

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Ajay Anant Ingle ,  Lucian Codrescu ,  David J. Hoyle ,  Jose Fridman ,  Marc M. Hoffman ,  Deepak Mathew

IPC: G06F9/30

CPC classification number: G06F9/3853

Abstract: An example method for executing multiple instructions in one or more slots includes receiving a packet including multiple instructions and executing the multiple instructions in one or more slots in a time shared manner. Each slot is associated with an execution data path or a memory data path. An example method for executing at least one instruction in a plurality of phases includes receiving a packet including an instruction, splitting the instruction into a plurality of phases, and executing the instruction in the plurality of phases.

Abstract translation: 用于在一个或多个时隙中执行多个指令的示例性方法包括接收包括多个指令的分组，并以时间共享的方式在一个或多个时隙中执行多个指令。 每个时隙与执行数据路径或存储器数据路径相关联。 用于执行多个阶段中的至少一个指令的示例性方法包括：接收包括指令的分组，将指令分解成多个阶段，以及执行多个阶段中的指令。

公开(公告)号：US09130786B2

公开(公告)日：2015-09-08

申请号：US13842663

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Deepak Mathew ,  Ajay Anant Ingle ,  Mao Zeng ,  Marc M. Hoffman

IPC: H04B1/00 ,  H04L27/00 ,  H04L25/02 ,  H04B1/7075 ,  H04B1/7093

CPC classification number: H04L25/0212 ,  H04B1/70752 ,  H04B1/7093 ,  H04B2201/70707

Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

Abstract translation: 一种装置包括选择逻辑，其被配置为选择存储在第一组寄存器中的第一组采样的第一子集。 第一子集包括存储在第一组寄存器的第一寄存器中的第一样本，并且还包括存储在第一组寄存器的第二寄存器上的第二样本。 该装置还包括移位逻辑，配置成移位存储在第二组寄存器中的第二组采样。 该装置还包括信道估计器，其被配置为基于第一子集生成与信道估计相关联的第一值，并且还基于所移位的第二组样本的第二子集。

公开(公告)号：US20150052330A1

公开(公告)日：2015-02-19

申请号：US13967191

申请日：2013-08-14

Applicant: QUALCOMM Incorporated

Inventor： Ajay Anant Ingle ,  Marc Murray Hoffman ,  Deepak Mathew ,  Mao Zeng

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897

Abstract: In a particular embodiment, a method includes executing a vector instruction at a processor. The vector instruction includes a vector input that includes a plurality of elements. Executing the vector instruction includes providing a first element of the plurality of elements as a first output. Executing the vector instruction further includes performing an arithmetic operation on the first element and a second element of the plurality of elements to provide a second output. Executing the vector instruction further includes storing the first output and the second output in an output vector.

Abstract translation: 在特定实施例中，一种方法包括在处理器处执行向量指令。 矢量指令包括包括多个元素的矢量输入。 执行向量指令包括提供多个元素中的第一元素作为第一输出。 执行向量指令还包括对第一元素和多个元素的第二元素执行算术运算以提供第二输出。 执行向量指令还包括将第一输出和第二输出存储在输出向量中。

公开(公告)号：US08943293B2

公开(公告)日：2015-01-27

申请号：US14219034

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Ajay Anant Ingle ,  Lucian Codrescu ,  Jian Shen

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34 ,  G06F12/08 ,  G06F17/50

CPC classification number: G06F12/0895 ,  G06F12/0802 ,  G06F12/0864 ,  G06F17/505 ,  G06F2212/2515 ,  G06F2212/601

Abstract: A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.

Abstract translation: 一种方法包括在高速缓存的标签状态阵列处接收地址，其中高速缓存可配置为具有小于第一大小的第一大小和第二大小。 所述方法还包括将所述地址的第一部分识别为设置索引，其中当所述高速缓冲存储器具有所述第一大小时，所述第一部分具有相同的位数，就像所述高速缓存具有所述第二大小一样。 所述方法还包括使用所述设置索引来定位所述标签状态阵列的至少一个标签字段，识别所述地址的第二部分以与存储在所述至少一个标签字段处的值进行比较，以定位所述标签状态阵列的至少一个状态字段 标签状态阵列，其与与第二部分匹配的特定标签字段相关联，基于当高速缓存具有该地址时，该地址的第三部分与至少一个状态字段的至少一个状态位的比较来识别高速缓存行 第二大小，并检索高速缓存行。

公开(公告)号：US09639503B2

公开(公告)日：2017-05-02

申请号：US13834785

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Ajay Anant Ingle ,  David J. Hoyle ,  Marc M. Hoffman

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/8053 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

公开(公告)号：US09606960B2

公开(公告)日：2017-03-28

申请号：US13834785

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Ajay Anant Ingle ,  David J. Hoyle ,  Marc M. Hoffman

IPC: G06F15/80 ,  G06F9/30

Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

公开(公告)号：US20140068225A1

公开(公告)日：2014-03-06

申请号：US14073190

申请日：2013-11-06

Applicant: QUALCOMM Incorporated

Inventor： Erich James Plondke ,  Ajay Anant Ingle ,  Lucian Codrescu ,  Paul D. Bassett

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A particular method includes receiving at least one translation lookaside buffer (TLB) configuration indicator. The at least one TLB configuration indicator indicates a specific number of entries to be enabled at a TLB. The method further includes modifying a number of searchable entries of the TLB in response to the at least one TLB configuration indicator.

Abstract translation: 一种特定的方法包括接收至少一个翻译后备缓冲器（TLB）配置指示符。 至少一个TLB配置指示符指示将在TLB处启用的特定数量的条目。 所述方法还包括响应于所述至少一个TLB配置指示符来修改所述TLB的可搜索条目的数量。