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    Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process
    1.
    发明授权
    Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process 有权
    在错误预测过程中预先计算直接分支部分目标地址的方法和装置

    公开(公告)号：US09489204B2

    公开(公告)日：2016-11-08

    申请号：US13842835

    申请日：2013-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Jiajin Tu ,  Suresh K. Venkumahanti ,  Brian R. Mestan

    IPC: G06F9/38 ,  G06F9/32

    CPC classification number: G06F9/3804 ,  G06F9/324 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3846 ,  G06F9/3861

    Abstract: An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also includes determining a partial target address using the destination address. The method further includes in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in an instruction cache with the partial target address.

    Abstract translation: 将部分目标地址存储在指令高速缓存中的示例性方法包括接收分支指令。 该方法还包括预测不采用分支指令的方向。 该方法还包括基于执行分支指令来计算目的地地址。 该方法还包括使用目的地址确定部分目标地址。 该方法还包括响应于从未被采取的转移指令的预测方向改变而取代指令高速缓存中的偏移与部分目标地址。

    Instruction cache having a multi-bit way prediction mask
    2.
    发明授权
    Instruction cache having a multi-bit way prediction mask 有权
    具有多位方式预测掩码的指令高速缓存

    公开(公告)号：US09304932B2

    公开(公告)日：2016-04-05

    申请号：US13721317

    申请日：2012-12-20

    Applicant: QUALCOMM Incorporated

    Inventor： Peter G. Sassone ,  Suresh K. Venkumahanti ,  Lucian Codrescu

    IPC: G06F12/00 ,  G06F12/08 ,  G06F9/38

    CPC classification number: G06F12/0875 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3832 ,  G06F12/0864 ,  G06F2212/6082 ,  Y02D10/13

    Abstract: In a particular embodiment, an apparatus includes control logic configured to selectively set bits of a multi-bit way prediction mask based on a prediction mask value. The control logic is associated with an instruction cache including a data array. A subset of line drivers of the data array is enabled responsive to the multi-bit way prediction mask. The subset of line drivers includes multiple line drivers.

    Abstract translation: 在特定实施例中，一种装置包括配置成基于预测掩模值有选择地设置多位方式预测掩模的比特的控制逻辑。 控制逻辑与包括数据阵列的指令高速缓存相关联。 数据阵列的线路驱动器的一个子集是响应于多位方式预测掩码启用的。 线路驱动器的子集包括多个线路驱动器。

    PARALLEL DISPATCH OF COPROCESSOR INSTRUCTIONS IN A MULTI-THREAD PROCESSOR
    6.
    发明申请
    PARALLEL DISPATCH OF COPROCESSOR INSTRUCTIONS IN A MULTI-THREAD PROCESSOR 审中-公开
    多线程处理器中的并联指令的并行分配

    公开(公告)号：US20140258680A1

    公开(公告)日：2014-09-11

    申请号：US13785017

    申请日：2013-03-05

    Applicant: QUALCOMM INCORPORATED

    Inventor： Ajay Anant Ingle ,  Lucian Codrescu ,  Suresh K. Venkumahanti ,  Jose Fridman

    IPC: G06F9/38

    CPC classification number: G06F9/3881 ,  G06F9/3802

    Abstract: Techniques are addressed for parallel dispatch of coprocessor and thread instructions to a coprocessor coupled to a threaded processor. A first packet of threaded processor instructions is accessed from an instruction fetch queue (IFQ) and a second packet of coprocessor instructions is accessed from the IFQ. The IFQ includes a plurality of thread queues that are each configured to store instructions associated with a specific thread of instructions. A dispatch circuit is configured to select the first packet of thread instructions from the IFQ and the second packet of coprocessor instructions from the IFQ and send the first packet to a threaded processor and the second packet to the coprocessor in parallel. A data port is configured to share data between the coprocessor and a register file in the threaded processor. Data port operations are accomplished without affecting operations on any thread executing on the threaded processor.

    Abstract translation: 解决了将协处理器和线程指令并行调度到耦合到线程处理器的协处理器的技术。 从指令队列（IFQ）访问第一个线程处理器指令包，并从IFQ访问第二个协处理器指令包。 IFQ包括多个线程队列，每个线程队列被配置为存储与特定指令线程相关联的指令。 调度电路被配置为从IFQ和来自IFQ的协处理器指令的第二分组选择线程指令的第一分组，并且将第一分组并行地发送到线程处理器，并将第二分组发送到协处理器。 数据端口被配置为在协处理器和线程处理器中的寄存器文件之间共享数据。 完成数据端口操作，而不影响在线程处理器上执行的任何线程的操作。

    INSTRUCTION CACHE HAVING A MULTI-BIT WAY PREDICTION MASK
    7.
    发明申请
    INSTRUCTION CACHE HAVING A MULTI-BIT WAY PREDICTION MASK 有权
    具有多点预测掩码的指令缓存

    公开(公告)号：US20140181405A1

    公开(公告)日：2014-06-26

    申请号：US13721317

    申请日：2012-12-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： Peter G. Sassone ,  Suresh K. Venkumahanti ,  Lucian Codrescu

    IPC: G06F12/08

    CPC classification number: G06F12/0875 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3832 ,  G06F12/0864 ,  G06F2212/6082 ,  Y02D10/13

    Abstract: In a particular embodiment, an apparatus includes control logic configured to selectively set bits of a multi-bit way prediction mask based on a prediction mask value. The control logic is associated with an instruction cache including a data array. A subset of line drivers of the data array is enabled responsive to the multi-bit way prediction mask. The subset of line drivers includes multiple line drivers.

    Abstract translation: 在特定实施例中，一种装置包括配置成基于预测掩模值有选择地设置多位方式预测掩模的比特的控制逻辑。 控制逻辑与包括数据阵列的指令高速缓存相关联。 数据阵列的线路驱动器的一个子集是响应于多位方式预测掩码启用的。 线路驱动器的子集包括多个线路驱动器。

    USING THE LEAST SIGNIFICANT BITS OF A CALLED FUNCTION'S ADDRESS TO SWITCH PROCESSOR MODES
    8.
    发明申请
    USING THE LEAST SIGNIFICANT BITS OF A CALLED FUNCTION'S ADDRESS TO SWITCH PROCESSOR MODES 审中-公开
    使用呼叫功能地址的最小重要位置切换处理器模式

    公开(公告)号：US20130205115A1

    公开(公告)日：2013-08-08

    申请号：US13655499

    申请日：2012-10-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： Charles Joseph Tabony ,  Erich James Plondke ,  Lucian Codrescu ,  Suresh K. Venkumahanti ,  Evandro Carlos Menezes

    IPC: G06F9/30 ,  G06F9/315

    CPC classification number: G06F9/30189 ,  G06F9/30054 ,  G06F9/30076 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/322 ,  G06F9/3816

    Abstract: Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.

    Abstract translation: 在处理系统中跟踪和切换执行模式的系统和方法。 处理系统被配置为在至少两个指令执行三极管中执行指令，包括从经典/对准模式和压缩/未对准模式选择的第一和第二执行模式。 所选择的指令（例如呼叫和返回）的目标地址在压缩模式下被强制地未对准，诸如压缩模式中的目标地址的最低有效位（对齐比特）之类的一个或多个比特与对应的比对比特不同 在经典模式下。 当在第一模式中执行期间遇到所选择的指令时，将操作切换到第二模式的决定是基于分析所选指令的目标地址的对准比特。

    Data cache way prediction
    9.
    发明授权
    Data cache way prediction 有权
    数据缓存方式预测

    公开(公告)号：US09367468B2

    公开(公告)日：2016-06-14

    申请号：US13741917

    申请日：2013-01-15

    Applicant: QUALCOMM Incorporated

    Inventor： Peter G. Sassone ,  Suresh K. Venkumahanti ,  Lucian Codrescu

    IPC: G06F12/16 ,  G06F12/08 ,  G06F9/345 ,  G06F9/38

    CPC classification number: G06F12/0864 ,  G06F9/3455 ,  G06F9/3832 ,  G06F2212/6082

    Abstract: In a particular embodiment, a method includes identifying one or more way prediction characteristics of an instruction. The method also includes selectively reading, based on identification of the one or more way prediction characteristics, a table to identify an entry of the table associated with the instruction that identifies a way of a data cache. The method further includes making a prediction whether a next access of the data cache based on the instruction will access the way.

    Abstract translation: 在特定实施例中，一种方法包括识别指令的一种或多种方式预测特性。 该方法还包括基于一个或多个方式预测特征的识别来选择性地读取用于标识与标识数据高速缓存的方式相关联的表的条目的表。 该方法还包括基于该指令来预测数据高速缓存的下一次访问是否将访问的方式。

    Overlap checking for a translation lookaside buffer (TLB)
    10.
    发明授权
    Overlap checking for a translation lookaside buffer (TLB) 有权
    翻译后备缓冲区（TLB）的重叠检查

    公开(公告)号：US09208102B2

    公开(公告)日：2015-12-08

    申请号：US13741981

    申请日：2013-01-15

    Applicant: QUALCOMM Incorporated

    Inventor： Suresh K. Venkumahanti ,  Erich J. Plondke ,  Lucian Codrescu ,  Shane M. Mahon ,  Rahul R. Toley ,  Fadi A. Hamdan

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F2212/652

    Abstract: An apparatus includes a translation lookaside buffer (TLB). The TLB includes at least one entry that includes an entry virtual address and an entry page size indication corresponding to an entry page. The apparatus also includes input logic configured to receive an input page size indication and an input virtual address corresponding to an input page. The apparatus further includes overlap checking logic configured to determine, based at least in part on the entry page size indication and the input page size indication, whether the input page overlaps the entry page.

    Abstract translation: 一种装置包括翻译后备缓冲器（TLB）。 TLB包括至少一个条目，其包括条目虚拟地址和对应于条目页面的条目页面大小指示。 该装置还包括被配置为接收输入页面大小指示和与输入页面相对应的输入虚拟地址的输入逻辑。 该装置还包括重叠检查逻辑，其被配置为至少部分地基于条目页面大小指示和输入页面大小指示来确定输入页面是否与入口页面重叠。

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