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    Sliding window operation
    1.
    发明授权
    Sliding window operation 有权

    公开(公告)号：US10459731B2

    公开(公告)日：2019-10-29

    申请号：US14803728

    申请日：2015-07-20

    Applicant: QUALCOMM Incorporated

    Inventor： Eric Mahurin ,  Jakub Pawel Golab

    IPC: G06F9/302 ,  G06F9/315 ,  G06F15/80 ,  G06F9/38 ,  G06F9/30 ,  G06F15/82

    Abstract: A first register has a lane storing first input data and a second register has a lane storing second input data elements. A width of the lane of the second register is equal to a width of the lane of the first register. A single-instruction-multiple-data (SIMD) lane has a lane width equal to the width of the lane of the first register. The SIMD lane is configured to perform a sliding window operation on the first input data elements in the lane of the first register and the second input data elements in the lane of the second register. Performing the sliding window operation includes determining a result based on a first input data element stored in a first position of the first register and a second input data element stored in a second position of the second register. The second position is different from the first position.

    System and method of floating point multiply operation processing
    2.
    发明授权
    System and method of floating point multiply operation processing 有权

    公开(公告)号：US10346133B1

    公开(公告)日：2019-07-09

    申请号：US15851390

    申请日：2017-12-21

    Applicant: QUALCOMM Incorporated

    Inventor： Albert Danysh ,  Erich Plondke ,  Eric Mahurin

    IPC: G06F7/487 ,  G06F7/485

    Abstract: A processor includes an integer multiplier configured to execute an integer multiply instruction to multiply significand bits of at least one floating point operand of a floating point multiply operation. The processor also includes a floating point multiplier configured to execute a special purpose floating point multiply accumulate instruction with respect to an intermediate result of the floating point multiply operation and the at least one floating point operand to generate a final floating point multiplication result.

    Data storage at contiguous memory addresses
    3.
    发明授权
    Data storage at contiguous memory addresses 有权

    公开(公告)号：US10162752B2

    公开(公告)日：2018-12-25

    申请号：US15273366

    申请日：2016-09-22

    Applicant: QUALCOMM Incorporated

    Inventor： Eric Mahurin ,  David Hoyle

    IPC: G06F12/00 ,  G06F12/06 ,  G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06F12/1009 ,  H03M7/30 ,  G06F13/00 ,  G06F13/28

    Abstract: A method for storing data at contiguous memory addresses includes, at a single-instruction-multiple-data (SIMD) processor, executing a parallel-prefix valid count instruction to determine a first offset of a first data vector and to determine a second offset of a second data vector that includes valid data and invalid data. The second offset is based on the first offset and a number of positions in the first data vector that are associated with valid data. The method also includes storing first valid data from the first data vector at a first memory address of a memory and storing second valid data from the second data vector at a particular memory address of the memory. The first memory address is based on the first offset and the particular memory address is based on the second offset.

    PIECEWISE POLYNOMIAL EVALUATION INSTRUCTION
    4.
    发明申请
    PIECEWISE POLYNOMIAL EVALUATION INSTRUCTION 审中-公开

    公开(公告)号：US20180081634A1

    公开(公告)日：2018-03-22

    申请号：US15273481

    申请日：2016-09-22

    Applicant: QUALCOMM Incorporated

    Inventor： Eric Mahurin ,  David Hoyle

    IPC: G06F7/544 ,  G06F7/57 ,  G06F9/30

    CPC classification number: G06F7/544 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/3004 ,  G06F17/17 ,  G06F2207/5354

    Abstract: A method includes retrieving, at a processor, a first instruction for performing a first piecewise Horner's method operation for a polynomial and executing the first instruction. Executing the first instruction causes the processor to perform operations including accessing one or more look-up tables based on an interval of a first function input to determine a first coefficient of the polynomial for the first input range. The operations also include determining a first partial polynomial output of the first piecewise Horner's method operation. Determining the first partial polynomial output includes multiplying a first partial polynomial input with the first function input to generate a first partial value and adding the first coefficient to the first partial value to determine the first partial polynomial output.

    System, apparatus, and method for a transient load instruction within a VLIW operation
    5.
    发明授权
    System, apparatus, and method for a transient load instruction within a VLIW operation 有权

    公开(公告)号：US11561792B2

    公开(公告)日：2023-01-24

    申请号：US14732784

    申请日：2015-06-08

    Applicant: QUALCOMM Incorporated

    Inventor： Eric Mahurin ,  Jakub Pawel Golab

    IPC: G06F9/30 ,  G06F9/38 ,  G06F1/10

    Abstract: A transient load instruction for a processor may include a transient or temporary load instruction that is executed in parallel with a plurality of input operands. The temporary load instruction loads a memory value into a temporary location for use within the instruction packet. According to some examples, a VLIW based microprocessor architecture may include a temporary cache for use in writing/reading a temporary memory value during a single VLIW packet cycle. The temporary cache is different from the normal register bank that does not allow writing and then reading the value just written during the same VLIW packet cycle.

    SLIDING WINDOW OPERATION
    7.
    发明申请
    SLIDING WINDOW OPERATION 审中-公开
    滑动窗口操作

    公开(公告)号：US20170024218A1

    公开(公告)日：2017-01-26

    申请号：US14803728

    申请日：2015-07-20

    Applicant: QUALCOMM Incorporated

    Inventor： Eric Mahurin ,  Jakub Pawel Golab

    IPC: G06F9/38 ,  G06F9/30 ,  G06F15/82

    Abstract: A first register has a lane storing first input data and a second register has a lane storing second input data elements. A width of the lane of the second register is equal to a width of the lane of the first register. A single-instruction-multiple-data (SIMD) lane has a lane width equal to the width of the lane of the first register. The SIMD lane is configured to perform a sliding window operation on the first input data elements in the lane of the first register and the second input data elements in the lane of the second register. Performing the sliding window operation includes determining a result based on a first input data element stored in a first position of the first register and a second input data element stored in a second position of the second register. The second position is different from the first position.

    Abstract translation: 第一寄存器具有存储第一输入数据的通道，第二寄存器具有存储第二输入数据元素的通道。 第二寄存器的通道的宽度等于第一寄存器的通道的宽度。 单指令多数据（SIMD）通道的通道宽度等于第一个寄存器的通道的宽度。 SIMD通道被配置为对第一寄存器的通道中的第一输入数据元素和第二寄存器的通道中的第二输入数据元素执行滑动窗口操作。 执行滑动窗口操作包括基于存储在第一寄存器的第一位置的第一输入数据元素和存储在第二寄存器的第二位置的第二输入数据元素来确定结果。 第二个位置与第一个位置不同。

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