公开(公告)号：US11200058B2

公开(公告)日：2021-12-14

申请号：US14271812

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Suresh Kumar Venkumahanti ,  Stephen Robert Shannon ,  Lin Wang

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50

Abstract: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.

公开(公告)号：US11074076B2

公开(公告)日：2021-07-27

申请号：US14271812

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Suresh Kumar Venkumahanti ,  Stephen Robert Shannon ,  Lin Wang

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50

Abstract: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.

公开(公告)号：US20190196867A1

公开(公告)日：2019-06-27

申请号：US15983992

申请日：2018-05-18

Applicant: QUALCOMM Incorporated

Inventor： Erich Plondke ,  Suresh Kumar Venkumahanti ,  Lin Wang ,  Lucian Codrescu

IPC: G06F9/48

CPC classification number: G06F9/4818 ,  G06F9/4812 ,  G06F9/4881

Abstract: A processor includes priority adjustment circuitry configured to adjust a priority of a thread of multiple threads configured to execute tasks to have a software-defined priority value or a designated high priority value. The processor also includes circuitry configured to identify a lowest priority thread of the multiple threads and a control unit configured to cause the lowest priority thread to take a pending interrupt.

公开(公告)号：US20150324239A1

公开(公告)日：2015-11-12

申请号：US14271812

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Suresh Kumar Venkumahanti ,  Stephen Robert Shannon ,  Lin Wang

IPC: G06F9/50 ,  G06F9/30

CPC classification number: G06F9/30098 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/5088

Abstract: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.

Abstract translation: 公开了使用共享硬件资源的集群处理器核心中的硬件线程的动态负载平衡以及相关电路，方法和计算机可读介质。 一方面，提供了包括控制单元的动态负载平衡电路。 控制单元被配置为确定集群处理器核心的第一集群和第二集群之间是否存在次优负载条件。 如果存在次优负载条件，则控制单元还被配置为经由共享硬件将第一集群的第一硬件线程的私有寄存器的内容传送到第二集群的第二硬件线程的私有寄存器 第一个硬件线程和第二个硬件线程的资源。 控制单元还被配置为经由共享硬件资源与第一硬件线程相关联的第一标识符与与第二硬件线程相关联的第二标识符进行交换。