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    DYNAMIC LOAD BALANCING OF HARDWARE THREADS IN CLUSTERED PROCESSOR CORES USING SHARED HARDWARE RESOURCES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA
    2.
    发明申请
    DYNAMIC LOAD BALANCING OF HARDWARE THREADS IN CLUSTERED PROCESSOR CORES USING SHARED HARDWARE RESOURCES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
    使用共享硬件资源的集群处理器芯片中的硬件线路的动态负载平衡以及相关电路，方法和计算机可读介质

    公开(公告)号：US20150324239A1

    公开(公告)日：2015-11-12

    申请号：US14271812

    申请日：2014-05-07

    Applicant: QUALCOMM Incorporated

    Inventor： Suresh Kumar Venkumahanti ,  Stephen Robert Shannon ,  Lin Wang

    IPC: G06F9/50 ,  G06F9/30

    CPC classification number: G06F9/30098 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/5088

    Abstract: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.

    Abstract translation: 公开了使用共享硬件资源的集群处理器核心中的硬件线程的动态负载平衡以及相关电路，方法和计算机可读介质。 一方面，提供了包括控制单元的动态负载平衡电路。 控制单元被配置为确定集群处理器核心的第一集群和第二集群之间是否存在次优负载条件。 如果存在次优负载条件，则控制单元还被配置为经由共享硬件将第一集群的第一硬件线程的私有寄存器的内容传送到第二集群的第二硬件线程的私有寄存器 第一个硬件线程和第二个硬件线程的资源。 控制单元还被配置为经由共享硬件资源与第一硬件线程相关联的第一标识符与与第二硬件线程相关联的第二标识符进行交换。

    Techniques for instruction perturbation for improved device security
    3.
    发明授权
    Techniques for instruction perturbation for improved device security 有权

    公开(公告)号：US11599625B2

    公开(公告)日：2023-03-07

    申请号：US17160769

    申请日：2021-01-28

    Applicant: QUALCOMM Incorporated

    Inventor： Arvind Krishnaswamy ,  Suresh Kumar Venkumahanti ,  Charles Tabony

    IPC: G06F21/00 ,  G06F21/52 ,  G06F9/38 ,  H04L49/00

    Abstract: Methods, systems, and devices for techniques for instruction perturbation for improved device security are described. A device may assign a set of executable instructions to an instruction packet based on a parameter associated with the instruction packet, and each executable instruction of the set of executable instructions may be independent from other executable instructions of the set of executable instructions. The device may select an order of the set of executable instructions based on a slot instruction rule associated with the device, and each executable instruction of the set of executable instructions may correspond to a respective slot associated with memory of the device. The device may modify the order of the set of executable instructions in a memory hierarchy post pre-decode based on the slot instruction rule and process the set of executable instructions of the instruction packet based on the modified order.

    Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media
    6.
    发明授权
    Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media 有权

    公开(公告)号：US11200058B2

    公开(公告)日：2021-12-14

    申请号：US14271812

    申请日：2014-05-07

    Applicant: QUALCOMM Incorporated

    Inventor： Suresh Kumar Venkumahanti ,  Stephen Robert Shannon ,  Lin Wang

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50

    Abstract: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.

    Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media
    7.
    发明授权
    Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media 有权

    公开(公告)号：US11074076B2

    公开(公告)日：2021-07-27

    申请号：US14271812

    申请日：2014-05-07

    Applicant: QUALCOMM Incorporated

    Inventor： Suresh Kumar Venkumahanti ,  Stephen Robert Shannon ,  Lin Wang

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50

    Abstract: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.

    System and method of VLIW instruction processing using reduced-width VLIW processor
    8.
    发明授权
    System and method of VLIW instruction processing using reduced-width VLIW processor 有权

    公开(公告)号：US10719325B2

    公开(公告)日：2020-07-21

    申请号：US15805935

    申请日：2017-11-07

    Applicant: QUALCOMM Incorporated

    Inventor： Peter Sassone ,  Christopher Koob ,  Suresh Kumar Venkumahanti

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.

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