公开(公告)号：US20230126322A1

公开(公告)日：2023-04-27

申请号：US17451988

申请日：2021-10-22

Applicant: QUALCOMM Incorporated

Inventor： Christopher Koob ,  Venkatarami Mora

IPC: G06F9/46 ,  G06F9/30 ,  G06F12/0891

Abstract: A device includes a processor coupled to a memory. The processor is configured to assign distinct domain identifiers to each of multiple software threads. The processor is also configured to control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.

公开(公告)号：US12175280B2

公开(公告)日：2024-12-24

申请号：US17451988

申请日：2021-10-22

Applicant: QUALCOMM Incorporated

Inventor： Christopher Koob ,  Venkatarami Mora

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/52 ,  G06F12/0891

Abstract: A device includes a processor coupled to a memory. The processor is configured to assign distinct domain identifiers to each of multiple software threads. The processor is also configured to control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.

公开(公告)号：US20200250101A1

公开(公告)日：2020-08-06

申请号：US16269399

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： GEORGE PATSILARAS ,  Wesley James Holland ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  Jeffrey Shabel ,  Simon Peter William Booth ,  Simo Petteri Kangaslampi ,  Christopher Koob ,  Wisnu Wurjantara ,  David Hansen ,  Ron Lieberman ,  Daniel Palermo ,  Colin Sharp ,  Hao Liu

IPC: G06F12/0893 ,  G06F12/06 ,  G06F3/06 ,  H03M7/30

Abstract: An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.

公开(公告)号：US11663011B2

公开(公告)日：2023-05-30

申请号：US16922885

申请日：2020-07-07

Applicant: QUALCOMM Incorporated

Inventor： Peter Sassone ,  Christopher Koob ,  Suresh Kumar Venkumahanti

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30196 ,  G06F9/384 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857

Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.

公开(公告)号：US10719325B2

公开(公告)日：2020-07-21

申请号：US15805935

申请日：2017-11-07

Applicant: QUALCOMM Incorporated

Inventor： Peter Sassone ,  Christopher Koob ,  Suresh Kumar Venkumahanti

IPC: G06F9/30 ,  G06F9/38

Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.