公开(公告)号：US20200250101A1

公开(公告)日：2020-08-06

申请号：US16269399

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： GEORGE PATSILARAS ,  Wesley James Holland ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  Jeffrey Shabel ,  Simon Peter William Booth ,  Simo Petteri Kangaslampi ,  Christopher Koob ,  Wisnu Wurjantara ,  David Hansen ,  Ron Lieberman ,  Daniel Palermo ,  Colin Sharp ,  Hao Liu

IPC: G06F12/0893 ,  G06F12/06 ,  G06F3/06 ,  H03M7/30

Abstract: An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.

公开(公告)号：US11256894B2

公开(公告)日：2022-02-22

申请号：US16703616

申请日：2019-12-04

Applicant: QUALCOMM Incorporated

Inventor： Wesley James Holland ,  Rashmi Kulkarni ,  Ling Feng Huang ,  Huang Huang ,  Jeffrey Shabel ,  Chih-Chi Cheng ,  Satish Anand ,  Songhe Cai ,  Simon Peter William Booth ,  Bohuslav Rychlik

IPC: G06K9/00 ,  G06F21/32 ,  G01N21/31 ,  H04L9/32

Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

公开(公告)号：US12224002B2

公开(公告)日：2025-02-11

申请号：US18313930

申请日：2023-05-08

Applicant: QUALCOMM Incorporated

Inventor： Wesley James Holland ,  Mehrad Tavakoli ,  Injoon Hong ,  Huang Huang ,  Simon Peter William Booth ,  Gerhard Reitmayr

IPC: G06F1/3287 ,  G06F3/01 ,  G06F3/14 ,  G06T5/80 ,  G06T19/00 ,  G11C11/412 ,  G11C11/419 ,  H10B10/00

Abstract: Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.

公开(公告)号：US11232834B2

公开(公告)日：2022-01-25

申请号：US16667754

申请日：2019-10-29

Applicant: QUALCOMM Incorporated

Inventor： Wesley James Holland ,  Mehrad Tavakoli ,  Injoon Hong ,  Huang Huang ,  Simon Peter William Booth ,  Gerhard Reitmayr

IPC: G06F1/3287 ,  G06F3/01 ,  G06F3/14 ,  G06T5/00 ,  G06T19/00 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.

公开(公告)号：US11016898B2

公开(公告)日：2021-05-25

申请号：US16543328

申请日：2019-08-16

Applicant: QUALCOMM INCORPORATED

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik ,  Wesley James Holland ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06F12/0868 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/121 ,  G06F12/0891 ,  G06F12/0871 ,  G06F12/1072

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

公开(公告)号：US10747671B1

公开(公告)日：2020-08-18

申请号：US16269440

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： Wesley James Holland ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  George Patsilaras ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06T1/60 ,  G06F12/0862 ,  G06F12/1009

Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

公开(公告)号：US10019380B2

公开(公告)日：2018-07-10

申请号：US14866228

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Serag Monier GadelRab ,  Jason Edward Podaima ,  Ruolong Liu ,  Alexander Miretsky ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Simon Peter William Booth ,  Meghal Varia ,  Thomas David Dryburgh

IPC: G06F12/00 ,  G06F12/1072 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/1072 ,  G06F2212/1008 ,  G06F2212/1016

Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.

公开(公告)号：US20170091116A1

公开(公告)日：2017-03-30

申请号：US14866228

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Serag Monier GadelRab ,  Jason Edward Podaima ,  Ruolong Liu ,  Alexander Miretsky ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Simon Peter William Booth ,  Meghal Varia ,  Thomas David Dryburgh

IPC: G06F12/10

CPC classification number: G06F12/1072 ,  G06F2212/1008 ,  G06F2212/1016

Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.

公开(公告)号：US12165550B2

公开(公告)日：2024-12-10

申请号：US18521414

申请日：2023-11-28

Applicant: QUALCOMM Incorporated

Inventor： Rakesh Raju Chenna Madhavuni ,  Wesley James Holland ,  Simon Peter William Booth

IPC: G09G3/00 ,  G02B27/00 ,  G02B27/01

Abstract: Aspects presented herein relate to methods, devices, and apparatuses for display processing. The apparatus may obtain a first intensity map associated with first luminance information for a scene. The apparatus may also configure a second intensity map based on the first intensity map and at least one coordinate frame from a perspective of a user of a device for display content associated with the scene. The apparatus may also determine whether luminance information for at least one region in the second intensity map is within a suitable luminance range for the display content associated with the scene. The apparatus may also process a set of pixels corresponding to a section in a display associated with the at least one region based on the luminance information being at least one of: within the suitable luminance range, outside of the suitable luminance range, or within an indistinguishable luminance range.

公开(公告)号：US20240370369A1

公开(公告)日：2024-11-07

申请号：US18484950

申请日：2023-10-11

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Sparsh Singhai ,  Subbarao Palacharla ,  Simon Peter William Booth ,  Girish Bhat ,  Ling Feng Huang ,  Scott Cheng ,  Yen-Kuan Wu ,  Mohammad Tamjidi

IPC: G06F12/06 ,  G06F12/0873

Abstract: Reconfigurable shared memory systems, and related processor-based systems and methods are disclosed. The reconfigurable shared memory system can be included in a processor-based system to provide memory for data storage. In exemplary aspects, the reconfigurable shared memory system not only includes the dedicated memory and the general memory (e.g., system cache memory), but also includes a reconfigurable memory. The reconfigurable memory can be configured as either part of addressable memory space of the dedicated memory if an application requires such additional dedicated memory, and/or configured as part of the addressable memory space of the general memory to provide additional memory to other clients for increased processing performance if such reconfigurable memory is not needed as part of the dedicated memory. The dedicated memory does not have to be sized to the worst-case size requirements of a given application.