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公开(公告)号：US12052023B1
公开(公告)日：2024-07-30
申请号：US18158662
申请日：2023-01-24
Applicant: QUALCOMM Incorporated
CPC classification number: H03L7/187 , H03L7/093 , H03L7/0992
Abstract: A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.
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2.发明授权公开(公告)号：US11863356B2
公开(公告)日：2024-01-02
申请号：US17589782
申请日：2022-01-31
Applicant: QUALCOMM Incorporated
Inventor： Miao Li , Zhiqin Chen , Yu Song , Hongmei Liao , Zhi Zhu , Hao Liu , Lejie Lu
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/03885
Abstract: A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.
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公开(公告)号：US11469730B2
公开(公告)日：2022-10-11
申请号：US17099183
申请日：2020-11-16
Applicant: QUALCOMM Incorporated
Abstract: A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.
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Patent Agency Ranking
公开(公告)号：US10992277B1
公开(公告)日：2021-04-27
申请号：US16785464
申请日：2020-02-07
Applicant: QUALCOMM Incorporated
Inventor： Li Sun , Dong Ren , Hao Liu , Sudheer Chowdary Gali
Abstract: Certain aspects are directed to an amplifier. The amplifier generally includes a first transistor having a gate coupled to an input node of the amplifier, a source degeneration circuit, and a second transistor coupled between the source degeneration circuit and a source of the first transistor, a gate of the second transistor being configured to receive a gain control signal from a controller.
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公开(公告)号：US11736069B2
公开(公告)日：2023-08-22
申请号：US17173947
申请日：2021-02-11
Applicant: QUALCOMM Incorporated
CPC classification number: H03F1/342 , H03F1/26 , H03F3/45475 , H03F3/45071 , H03F3/45179 , H03F2200/372
Abstract: An amplifier has a first amplifying circuit configured to receive a voltage input and to output an amplified current, a second amplifying circuit configured to receive the amplified current and to output an amplified voltage, the second amplifying circuit comprising a pair of feedback resistive elements, each feedback resistive element being coupled to a gate and drain of a corresponding transistor in a pair of output transistors in the second amplifying circuit, and a feedback circuit configured to provide a negative feedback loop between an input and an output of the pair of output transistors, the feedback circuit including a first transconductance amplification circuit and a first equalizing circuit.
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公开(公告)号：US10972108B1
公开(公告)日：2021-04-06
申请号：US16864652
申请日：2020-05-01
Applicant: QUALCOMM Incorporated
Abstract: A clock system including: an in-phase clock input and an in-phase clock output; a quadrature clock input and a quadrature clock output; a control loop configured to receive the in-phase clock output and the quadrature clock output, the control loop including a Boolean logic gate coupled to an operational amplifier (op-amp) through a low-pass filter; and an analog delay element coupled between the quadrature clock input and the quadrature clock output, the analog delay element comprising a plurality of capacitors.
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公开(公告)号：US20200250101A1
公开(公告)日：2020-08-06
申请号：US16269399
申请日：2019-02-06
Applicant: QUALCOMM INCORPORATED
Inventor： GEORGE PATSILARAS , Wesley James Holland , Bohuslav Rychlik , Andrew Edmund Turner , Jeffrey Shabel , Simon Peter William Booth , Simo Petteri Kangaslampi , Christopher Koob , Wisnu Wurjantara , David Hansen , Ron Lieberman , Daniel Palermo , Colin Sharp , Hao Liu
IPC: G06F12/0893 , G06F12/06 , G06F3/06 , H03M7/30
Abstract: An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.
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公开(公告)号：US11923861B1
公开(公告)日：2024-03-05
申请号：US18164211
申请日：2023-02-03
Applicant: QUALCOMM Incorporated
CPC classification number: H03L7/0995 , H03L7/0891 , H03L7/091
Abstract: A voltage controlled oscillator (VCO), including: at least one second upper voltage rail; at least one second lower voltage rail; a ring of N cascaded inverters, wherein the set of N cascaded inverters are coupled between the at least one second upper voltage rail and the at least one second lower voltage rail; at least one first frequency band select circuit coupled between first upper voltage rail and the at least one second upper voltage rail; at least one second frequency band select circuit coupled between the at least one second lower voltage rail and first lower voltage rail; at least one first VCO frequency control circuit coupled between the first upper voltage rail and the at least one second upper voltage rail; and at least one second VCO frequency control circuit coupled between the at least one second lower voltage rail and the first lower voltage rail.
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