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    Linearity of phase interpolators by combining current coding and size coding
    2.
    发明授权
    Linearity of phase interpolators by combining current coding and size coding 有权
    通过组合当前编码和大小编码来实现相位内插器的线性度

    公开(公告)号：US09485084B2

    公开(公告)日：2016-11-01

    申请号：US14300127

    申请日：2014-06-09

    Applicant: Qualcomm Incorporated

    Inventor： Li Sun ,  Zhi Zhu ,  Xiaohua Kong ,  Kenneth Luis Arcudia ,  Zhiqin Chen

    IPC: H04L7/033 ,  H03L7/099 ,  H03K5/135 ,  H03K5/00

    CPC classification number: H04L7/0331 ,  H03K5/135 ,  H03K2005/00065 ,  H03L7/099

    Abstract: A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.

    Abstract translation: 一种相位插值器，包括：包括第一多个分支和多个尾电流源的第一部分，每个分支包括差分对晶体管，所述差分对晶体管的源极端子连接以形成源节点，其中每个尾部 电流源耦合到源节点之一，并且其中所述差分对晶体管和相应的尾电流源以当前编码方案配置; 第二部分包括第二多个分支和耦合到第二多个分支的固定电流源，第二多个分支的每个分支包括第二多个差分对晶体管和多个开关，其以尺寸编码方案 ; 其中所述第一部分和所述第二部分彼此耦合并耦合到一对负载电阻器。

    High-speed sampler
    3.
    发明授权
    High-speed sampler 有权

    公开(公告)号：US12009811B2

    公开(公告)日：2024-06-11

    申请号：US18327832

    申请日：2023-06-01

    Applicant: QUALCOMM Incorporated

    Inventor： Chiu Keung Tang ,  Zhiqin Chen

    IPC: G11C7/06 ,  G11C27/02 ,  H03K17/687 ,  H03K19/20

    CPC classification number: H03K17/6872 ,  G11C7/06 ,  G11C27/02 ,  H03K17/6874 ,  H03K19/20

    Abstract: A regeneration circuit includes a first inverting circuit, a second inverting circuit, a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit. The regeneration circuit also includes a third transistor including a gate coupled to a gate of the first transistor, a first switch configured to couple the third transistor to the input of the second inverting circuit based on a voltage of the first inverting circuit, a fourth transistor including a gate coupled to a gate of the second transistor, and a second switch configured to couple the fourth transistor to the input of the first inverting circuit based on a voltage of the second inverting circuit.

    Delay cell for quadrature clock generation with insensitivity to PVT variation and equal rising/falling edges
    4.
    发明授权
    Delay cell for quadrature clock generation with insensitivity to PVT variation and equal rising/falling edges 有权

    公开(公告)号：US11329639B1

    公开(公告)日：2022-05-10

    申请号：US17212366

    申请日：2021-03-25

    Applicant: QUALCOMM Incorporated

    Inventor： Chiu Keung Tang ,  Zhiqin Chen

    IPC: H03K5/13 ,  H03K5/156 ,  H03K5/00

    Abstract: A novel delay circuit for quadrature clock generation with insensitivity to process, voltage, temperature (PVT) variations and equal rising/falling edges is disclosed. In one implementation, the delay circuit includes a first N-substage having a sinking current source, configured to receive an input signal and to generate a rising edge of an output signal of the delay circuit, wherein the output signal is a delayed version of the input signal. The delay circuit further includes a first P-substage having a sourcing current source, configured to receive the input signal and to generate a falling edge of the output signal, where the sinking current source and the sourcing current source are variable in response to respective ones of a plurality of bias voltages.

    Circuit for generating accurate clock phase signals for high-speed SERDES
    5.
    发明授权
    Circuit for generating accurate clock phase signals for high-speed SERDES 有权
    用于为高速SERDES产生精确时钟相位信号的电路

    公开(公告)号：US09225324B2

    公开(公告)日：2015-12-29

    申请号：US14257913

    申请日：2014-04-21

    Applicant: QUALCOMM Incorporated

    Inventor： Kenneth Arcudia ,  Zhiqin Chen

    IPC: H03M9/00 ,  H03K5/156 ,  H03L7/06

    CPC classification number: H03K5/1565 ,  H03L7/06 ,  H03L7/0807 ,  H03L7/0812 ,  H03M9/00

    Abstract: Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter converts the differential CML clock signals to differential CMOS clock signals and provides duty cycle correction. Delay cells produce delayed clock signals from the differential CMOS clock signals. The differential CMOS clock signals and the delayed clock signals are logically combined to produce four quarter clock signals having active times of one-quarter clock period. Set-reset latches produce the four clock signals from the quarter clock signals. A calibration module control delays of the delay cells and controls the duty cycle correction of the CML to CMOS converter to adjust the timing relationships of the four clock signals. The four clock signals may be used, for example, in a deserializer.

    Abstract translation: 公开了用于产生具有精确定时关系的时钟相位信号的系统和方法。 例如，可以从差分CML时钟信号产生间隔90度的四个时钟信号。 CML到CMOS转换器将差分CML时钟信号转换为差分CMOS时钟信号，并提供占空比校正。 延迟单元从差分CMOS时钟信号产生延迟的时钟信号。 差分CMOS时钟信号和延迟的时钟信号被逻辑地组合以产生具有四分之一时钟周期的有效时间的四分之四四个时钟信号。 设置复位锁存器从四分之一时钟信号产生四个时钟信号。 校准模块控制延迟单元的延迟，并控制CML到CMOS转换器的占空比校正，以调整四个时钟信号的时序关系。 四个时钟信号可以例如在解串器中使用。

    Linearity of Phase Interpolators by Combining Current Coding and Size Coding
    6.
    发明申请
    Linearity of Phase Interpolators by Combining Current Coding and Size Coding 有权
    通过组合当前编码和大小编码的相位插值器的线性度

    公开(公告)号：US20150358148A1

    公开(公告)日：2015-12-10

    申请号：US14300127

    申请日：2014-06-09

    Applicant: Qualcomm Incorporated

    Inventor： Li Sun ,  Zhi Zhu ,  Xiaohua Kong ,  Kenneth Luis Arcudia ,  Zhiqin Chen

    IPC: H04L7/033 ,  H03L7/099

    CPC classification number: H04L7/0331 ,  H03K5/135 ,  H03K2005/00065 ,  H03L7/099

    Abstract: A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.

    Abstract translation: 一种相位插值器，包括：包括第一多个分支和多个尾电流源的第一部分，每个分支包括差分对晶体管，所述差分对晶体管的源极端子连接以形成源节点，其中每个尾部 电流源耦合到源节点之一，并且其中所述差分对晶体管和相应的尾电流源以当前编码方案配置; 第二部分包括第二多个分支和耦合到第二多个分支的固定电流源，第二多个分支的每个分支包括第二多个差分对晶体管和多个开关，其以尺寸编码方案 ; 其中所述第一部分和所述第二部分彼此耦合并耦合到一对负载电阻器。

    Early lock detection for phase locked loops
    7.
    发明授权
    Early lock detection for phase locked loops 有权

    公开(公告)号：US12255661B1

    公开(公告)日：2025-03-18

    申请号：US18537304

    申请日：2023-12-12

    Applicant: QUALCOMM Incorporated

    Inventor： Julian Puscar ,  Burcin Serter Ergun ,  Brett Patrick Delaney ,  Zhiqin Chen

    IPC: H03L7/095 ,  H03L7/18

    Abstract: A method for calibrating a phase locked loop (PLL) includes counting cycles of an output clock signal generated by the PLL until early phase lock signal is asserted when the cycles of the output clock signal counted within a first duration of time differ from a first target value by no more than a first maximum difference, counting cycles of the output clock signal until final phase lock signal is asserted when the cycles of the output clock signal counted within a second duration of time differ from a second target value by no more than a second maximum difference, the second duration of time being greater than the first duration of time, and using the output clock signal to control an operation in a physical layer circuit of a communication interface after the early phase lock signal is asserted and before the final phase lock signal is asserted.

    Frequency power manager
    10.
    发明授权
    Frequency power manager 有权
    频率功率管理器

    公开(公告)号：US09305632B2

    公开(公告)日：2016-04-05

    申请号：US13901511

    申请日：2013-05-23

    Applicant: QUALCOMM Incorporated

    Inventor： Zeeshan Shafaq Syed ,  Nan Chen ,  Yong Xu ,  Michael Thomas Fertsch ,  Boris Dimitrov Andreev ,  Zhiqin Chen ,  Chang Ki Kwon

    IPC: G06F1/32 ,  G11C11/4074

    CPC classification number: G11C11/4074 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

    Abstract translation: 提供了一种方法和装置。 该装置是控制多个模块的功率模式的硬件模块。 该装置接收到期望的操作频率的指示。 基于接收到的指示，设备确定从与第一组模块相关联的第一功率模式切换到对应于期望操作频率并与第二组模块相关联的第二功率模式。 该装置使得与第一功率模式不相关的第二组模块中的模块在启用与第一功率模式不相关的第二组模块中的模块之后的一段时间期满后停止通过多个模块的业务 通过第二组模块路由流量，并禁用与第二功率模式无关的第一组模块中的模块。

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