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    Digital-to-phase converter
    2.
    发明授权
    Digital-to-phase converter 有权
    数模转换器

    公开(公告)号：US09484900B2

    公开(公告)日：2016-11-01

    申请号：US14535744

    申请日：2014-11-07

    Applicant: QUALCOMM Incorporated

    Inventor： Hanan Cohen

    IPC: H03H11/16 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081 ,  H03K5/00

    CPC classification number: H03K5/135 ,  H03K2005/00286 ,  H03L7/00 ,  H03L7/0812

    Abstract: Systems and methods for converting digital signals into clock phases are disclosed. An example digital-to-phase converter circuit receives a complementary in-phase and quadrature clock signals and produces four clock outputs at a phase controlled by a digital phase control input. The digital-to-phase converter uses first and second pre-driver modules to buffer the -phase and quadrature clock signals and produce corresponding buffered clock signals having controlled slew rates. Mixer modules produce the clock outputs by forming weighted combinations of the buffered clock signals. The weighting is determined based on the phase control input. The controlled slew rates of the buffered clock signals allow digital mixer module to provide accurate phase control. The digital-to-phase converter may also include an output buffer that compensates for nonlinearities in the relationship between the phases of the clock outputs and the phase control input.

    Abstract translation: 公开了将数字信号转换成时钟相位的系统和方法。 一个示例性数字 - 相位转换器电路接收互补的同相和正交时钟信号，并在由数字相位控制输入控制的相位产生四个时钟输出。 数/模转换器使用第一和第二预驱动器模块来缓冲相位和正交时钟信号，并产生具有受控转换速率的对应缓冲时钟信号。 混频器模块通过形成缓冲时钟信号的加权组合来产生时钟输出。 加权根据相位控制输入确定。 缓冲时钟信号的受控转换速率允许数字混频器模块提供精确的相位控制。 数/模转换器还可以包括输出缓冲器，其补偿时钟输出的相位和相位控制输入之间的关系中的非线性。

    NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE
    4.
    发明申请
    NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE 有权
    新的相位锁相环（PLL）架构

    公开(公告)号：US20170041005A1

    公开(公告)日：2017-02-09

    申请号：US14820894

    申请日：2015-08-07

    Applicant: QUALCOMM Incorporated

    Inventor： Bupesh Pandita ,  Hanan Cohen ,  Eskinder Hailu ,  Kenneth Luis Arcudia

    IPC: H03K21/10

    CPC classification number: H03K21/10 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03L7/1976

    Abstract: In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

    Abstract translation: 在一个实施例中，用于分频的方法包括将模数信号向上传播到一级级联分频器级从最后一级分频级到第一分频级，并且对于每个分频级，产生相应的本地 当模数信号传播到分频器级之后的负载信号。 该方法还包括对于每个分频器级，基于相应的本地负载信号将一个或多个相应的控制位输入到分频器级，所述一个或多个相应的控制位设置分频器级的分频器值。

    DIGITAL-TO-PHASE CONVERTER
    5.
    发明申请
    DIGITAL-TO-PHASE CONVERTER 有权
    数字到相位转换器

    公开(公告)号：US20160134266A1

    公开(公告)日：2016-05-12

    申请号：US14535744

    申请日：2014-11-07

    Applicant: QUALCOMM Incorporated

    Inventor： Hanan Cohen

    IPC: H03K5/135 ,  H03L7/081

    CPC classification number: H03K5/135 ,  H03K2005/00286 ,  H03L7/00 ,  H03L7/0812

    Abstract: Systems and methods for converting digital signals into clock phases are disclosed. An example digital-to-phase converter circuit receives a complementary in-phase and quadrature clock signals and produces four clock outputs at a phase controlled by a digital phase control input. The digital-to-phase converter uses first and second pre-driver modules to buffer the -phase and quadrature clock signals and produce corresponding buffered clock signals having controlled slew rates. Mixer modules produce the clock outputs by forming weighted combinations of the buffered clock signals. The weighting is determined based on the phase control input. The controlled slew rates of the buffered clock signals allow digital mixer module to provide accurate phase control. The digital-to-phase converter may also include an output buffer that compensates for nonlinearities in the relationship between the phases of the clock outputs and the phase control input.

    Abstract translation: 公开了将数字信号转换成时钟相位的系统和方法。 一个示例性数字 - 相位转换器电路接收互补的同相和正交时钟信号，并在由数字相位控制输入控制的相位产生四个时钟输出。 数/模转换器使用第一和第二预驱动器模块来缓冲相位和正交时钟信号，并产生具有受控转换速率的对应缓冲时钟信号。 混频器模块通过形成缓冲时钟信号的加权组合来产生时钟输出。 加权根据相位控制输入确定。 缓冲时钟信号的受控转换速率允许数字混频器模块提供精确的相位控制。 数/模转换器还可以包括输出缓冲器，其补偿时钟输出的相位和相位控制输入之间的关系中的非线性。

    Fractional phase locked loop (PLL) architecture
    9.
    发明授权
    Fractional phase locked loop (PLL) architecture 有权
    分数锁相环（PLL）架构

    公开(公告)号：US09577646B1

    公开(公告)日：2017-02-21

    申请号：US14820894

    申请日：2015-08-07

    Applicant: QUALCOMM Incorporated

    Inventor： Bupesh Pandita ,  Hanan Cohen ,  Eskinder Hailu ,  Kenneth Luis Arcudia

    IPC: H03K21/10

    CPC classification number: H03K21/10 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03L7/1976

    Abstract: In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

    Abstract translation: 在一个实施例中，用于分频的方法包括将模数信号向上传播到一级级联分频器级从最后一级分频级到第一分频级，并且对于每个分频级，产生相应的本地 当模数信号传播到分频器级之后的负载信号。 该方法还包括对于每个分频器级，基于相应的本地负载信号将一个或多个相应的控制位输入到分频器级，所述一个或多个相应的控制位设置分频器级的分频器值。

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