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    Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibration
    1.
    发明授权
    Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibration 有权

    公开(公告)号：US09998126B1

    公开(公告)日：2018-06-12

    申请号：US15644426

    申请日：2017-07-07

    Applicant: QUALCOMM Incorporated

    Inventor： Eskinder Hailu ,  Bupesh Pandita

    IPC: H03L7/085 ,  G04F10/00

    CPC classification number: H03L7/085 ,  G04F10/00 ,  G04F10/005 ,  H03L7/0814

    Abstract: Aspects of the disclosure are directed to generating a quadrature clock signal from an in-phase clock signal. In accordance with one aspect, a delay locked loop (DLL), including a first pulse to digital converter (PDC) to generate a first pulse width measurement, wherein the first pulse width measurement includes a first sign and a first magnitude; a second pulse to digital converter (PDC) to generate a second pulse width measurement, wherein the second pulse width measurement includes a second sign and a second magnitude; a digital loop filter coupled to the first PDC and the second PDC, the digital loop filter to generate a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and a first delay generation block to generate a quadrature clock signal based on the filtered comparison output and an in-phase clock signal.

    NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE
    2.
    发明申请
    NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE 有权
    新的相位锁相环（PLL）架构

    公开(公告)号：US20170041005A1

    公开(公告)日：2017-02-09

    申请号：US14820894

    申请日：2015-08-07

    Applicant: QUALCOMM Incorporated

    Inventor： Bupesh Pandita ,  Hanan Cohen ,  Eskinder Hailu ,  Kenneth Luis Arcudia

    IPC: H03K21/10

    CPC classification number: H03K21/10 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03L7/1976

    Abstract: In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

    Abstract translation: 在一个实施例中，用于分频的方法包括将模数信号向上传播到一级级联分频器级从最后一级分频级到第一分频级，并且对于每个分频级，产生相应的本地 当模数信号传播到分频器级之后的负载信号。 该方法还包括对于每个分频器级，基于相应的本地负载信号将一个或多个相应的控制位输入到分频器级，所述一个或多个相应的控制位设置分频器级的分频器值。

    Apparatus and method for frequency calibration of voltage controlled oscillator (VCO) including determining VCO frequency range
    4.
    发明授权
    Apparatus and method for frequency calibration of voltage controlled oscillator (VCO) including determining VCO frequency range 有权

    公开(公告)号：US10355701B2

    公开(公告)日：2019-07-16

    申请号：US15675160

    申请日：2017-08-11

    Applicant: QUALCOMM Incorporated

    Inventor： Bupesh Pandita ,  Eskinder Hailu ,  Zhuo Gao

    IPC: H03L7/089 ,  H03L7/087 ,  H03L7/099 ,  H03L7/095 ,  H03B5/12 ,  G06F1/10 ,  H03K3/03

    Abstract: A phase lock loop (PLL) circuit includes a selection mode device before a phase detector and time-to-digital converter (TDC). In a first mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the reference clock signal. In a second mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the feedback clock signal. In a third mode, the selection mode device outputs the reference and feedback clock signals. The phase detector and TDC are configured to generate a signal: indicating the reference clock frequency in the first mode; indicating of the feedback clock frequency in the second mode; and indicating a phase/frequency difference between the feedback and reference clocks in the third mode. These signals are used to control a VCO clock signal.

    Apparatus and method for in situ analog signal diagnostic and debugging with calibrated analog-to-digital converter
    5.
    发明授权
    Apparatus and method for in situ analog signal diagnostic and debugging with calibrated analog-to-digital converter 有权

    公开(公告)号：US09729163B1

    公开(公告)日：2017-08-08

    申请号：US15251861

    申请日：2016-08-30

    Applicant: QUALCOMM Incorporated

    Inventor： Deqiang Song ,  Xiaohua Kong ,  Bupesh Pandita ,  Zhuo Gao

    IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12

    CPC classification number: H03M1/06 ,  G01R31/316 ,  G01R31/3167 ,  H03M1/1009 ,  H03M1/12

    Abstract: An integrated circuit (IC) chip includes an on-chip analog signal monitoring circuit for monitoring a set of analog signals generated by one or more mixed signal cores within the IC chip, converting the analog signals into digital signals, storing the digital signals in an on-chip memory, and providing the digital signals to a test equipment upon request. The analog signal monitoring signal includes an on-chip reference generator for generating precise voltages and/or currents, a switching network for routing a selected reference signal to an analog-to-digital converter (ADC) for calibration purpose and for routing a selected analog signal from one of the mixed signal cores to the ADC for digitizing purposes. The IC chip further includes an on-chip memory for storing the digitized analog signals for subsequent accessing by a test equipment for analysis. The IC chip includes a digital analog test point (ATP) for outputting the digitized analog signals.

    Phase locked loop (PLL) architecture
    8.
    发明授权
    Phase locked loop (PLL) architecture 有权
    锁相环（PLL）架构

    公开(公告)号：US09485085B2

    公开(公告)日：2016-11-01

    申请号：US14644029

    申请日：2015-03-10

    Applicant: QUALCOMM, Incorporated

    Inventor： Kenneth Luis Arcudia ,  Jeffrey Andrew Shafer ,  Bupesh Pandita

    IPC: H04L7/033 ,  H04L7/04 ,  H04L7/00 ,  H03B5/12

    CPC classification number: H04L7/0332 ,  H03B5/1212 ,  H03B5/1228 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0025 ,  H04L7/041

    Abstract: In one embodiment, a phase locked loop (PLL) comprises a voltage-controlled oscillator (VCO), a frequency divider configured to frequency divide an output signal of the VCO to produce a feedback signal, and a phase detection circuit configured to detect a phase difference between a reference signal and the feedback signal, and to generate an output signal based on the detected phase difference. The PLL also comprises a proportional circuit configured to generate a control voltage based on the output signal of the phase detection circuit, wherein the control voltage tunes a first capacitance of the VCO to provide phase correction. The PLL further comprises an integration circuit configured to convert the control voltage into a digital signal, to integrate the digital signal, and to tune a second capacitance of the VCO based on the integrated digital signal to provide frequency tracking.

    Abstract translation: 在一个实施例中，锁相环（PLL）包括压控振荡器（VCO），分频器，被配置为频率分频VCO的输出信号以产生反馈信号;以及相位检测电路，被配置为检测相位 参考信号和反馈信号之间的差异，并且基于检测到的相位差产生输出信号。 PLL还包括比例电路，其被配置为基于相位检测电路的输出信号产生控制电压，其中控制电压调谐VCO的第一电容以提供相位校正。 PLL还包括集成电路，其被配置为将控制电压转换为数字信号，以集成数字信号，并且基于积分数字信号来调谐VCO的第二电容以提供频率跟踪。

    NOVEL PHASE LOCKED LOOP (PLL) ARCHITECTURE
    9.
    发明申请
    NOVEL PHASE LOCKED LOOP (PLL) ARCHITECTURE 有权
    新型锁相环（PLL）架构

    公开(公告)号：US20160269172A1

    公开(公告)日：2016-09-15

    申请号：US14644029

    申请日：2015-03-10

    Applicant: QUALCOMM, Incorporated

    Inventor： Kenneth Luis Arcudia ,  Jeffrey Andrew Shafer ,  Bupesh Pandita

    IPC: H04L7/033 ,  H04L7/00 ,  H03B5/12 ,  H04L7/04

    CPC classification number: H04L7/0332 ,  H03B5/1212 ,  H03B5/1228 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0025 ,  H04L7/041

    Abstract: In one embodiment, a phase locked loop (PLL) comprises a voltage-controlled oscillator (VCO), a frequency divider configured to frequency divide an output signal of the VCO to produce a feedback signal, and a phase detection circuit configured to detect a phase difference between a reference signal and the feedback signal, and to generate an output signal based on the detected phase difference. The PLL also comprises a proportional circuit configured to generate a control voltage based on the output signal of the phase detection circuit, wherein the control voltage tunes a first capacitance of the VCO to provide phase correction. The PLL further comprises an integration circuit configured to convert the control voltage into a digital signal, to integrate the digital signal, and to tune a second capacitance of the VCO based on the integrated digital signal to provide frequency tracking.

    Abstract translation: 在一个实施例中，锁相环（PLL）包括压控振荡器（VCO），分频器，被配置为频率分频VCO的输出信号以产生反馈信号;以及相位检测电路，被配置为检测相位 参考信号和反馈信号之间的差异，并且基于检测到的相位差产生输出信号。 PLL还包括比例电路，其被配置为基于相位检测电路的输出信号产生控制电压，其中控制电压调谐VCO的第一电容以提供相位校正。 PLL还包括集成电路，其被配置为将控制电压转换为数字信号，以集成数字信号，并且基于积分数字信号来调谐VCO的第二电容以提供频率跟踪。

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