公开(公告)号：US09793337B2

公开(公告)日：2017-10-17

申请号：US15167783

申请日：2016-05-27

Applicant: MediaTek Inc.

Inventor： Yuan-Fu Chung ,  Chu-Wei Hu ,  Yuan-Hung Chung

IPC: H01L21/70 ,  H01L49/02 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28 ,  H01L21/324 ,  H01L27/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L21/02 ,  H01L21/266 ,  H01L29/167 ,  H01L21/3215 ,  H01L27/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.

公开(公告)号：US20130271213A1

公开(公告)日：2013-10-17

申请号：US13792224

申请日：2013-03-11

Applicant: MEDIATEK INC.

Inventor： Yuan-Hung Chung ,  Yi-Shing Shih

IPC: H03F1/26

CPC classification number: H04B1/12 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03F1/26 ,  H03F1/56 ,  H03F3/19 ,  H03F3/45475 ,  H03F2200/294 ,  H04L25/0278

Abstract: A signal processing circuit with noise cancellation includes an impedance matching unit and a transconductance stage. The impedance matching unit is disposed at a first path, and arranged to provide input impedance matching, wherein the impedance matching unit is a bilateral element, and the first path is coupled between a signal input port and a signal output port. The transconductance stage is disposed at a second path, and arranged to guide circuit introduced noise to the signal output port for noise cancellation at the signal output port, wherein the second path is coupled between the signal input port and the signal output port.

Abstract translation: 具有噪声消除的信号处理电路包括阻抗匹配单元和跨导级。 阻抗匹配单元设置在第一路径处，并且被布置成提供输入阻抗匹配，其中阻抗匹配单元是双向元件，并且第一路径耦合在信号输入端口和信号输出端口之间。 跨导级设置在第二路径处，并且被布置成引导电路引入的噪声到信号输出端口用于信号输出端口处的噪声消除，其中第二路径耦合在信号输入端口和信号输出端口之间。

公开(公告)号：US10096543B2

公开(公告)日：2018-10-09

申请号：US14748161

申请日：2015-06-23

Applicant: MEDIATEK INC.

Inventor： Chien-Kai Huang ,  Yuan-Fu Chung ,  Yuan-Hung Chung

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L23/522 ,  H01L49/02

Abstract: The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer and a first dielectric layer. The first metal layer is arranged to be a part of a first electrode of the semiconductor capacitor structure, and the first metal layer comprises a first portion and a second portion. The first portion is formed to have a first pattern, and the second portion is connected to the first portion. The second metal layer is arranged to be a part of a second electrode of the semiconductor capacitor structure, and the first dielectric layer is formed between the first metal layer and the second metal layer.

公开(公告)号：US08970997B2

公开(公告)日：2015-03-03

申请号：US13662851

申请日：2012-10-29

Applicant: MediaTek Inc.

Inventor： Bo-Shih Huang ,  Tsung-Ming Chen ,  Yuan-Hung Chung

IPC: H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06 ,  H02H3/20 ,  H02H9/04

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line.

公开(公告)号：US20180124704A1

公开(公告)日：2018-05-03

申请号：US15342125

申请日：2016-11-03

Applicant: MEDIATEK INC.

Inventor： Shih-Ching Jung ,  Chee-Lee Heng ,  Shang-Wei Huang ,  Shu-Liang Lee ,  Yuan-Hung Chung

IPC: H04W52/02

CPC classification number: H04W52/0229 ,  H04W52/0212 ,  H04W84/12 ,  Y02D70/00 ,  Y02D70/10 ,  Y02D70/14 ,  Y02D70/142 ,  Y02D70/26

Abstract: A method of wake-up signal transmission for an access point (AP) in a wireless communication system is disclosed. The method comprises transmitting a beacon for notification of a Wi-Fi device in the wireless communication system, and transmitting a wake-up signal to the Wi-Fi device, wherein the wake-up signal is a binary signal for indicating the Wi-Fi device to receive or not to receive a data from the AP.

公开(公告)号：US09379175B2

公开(公告)日：2016-06-28

申请号：US14557743

申请日：2014-12-02

Applicant: MediaTek Inc.

Inventor： Yuan-Fu Chung ,  Chu-Wei Hu ,  Yuan-Hung Chung

IPC: H01L21/02 ,  H01L49/02 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28 ,  H01L21/324 ,  H01L27/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L21/266 ,  H01L29/167 ,  H01L27/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. Furthermore, a method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.

Abstract translation: 集成电路包括在基板上形成的具有第一晶粒尺寸的第一多晶硅区域。 集成电路还包括形成在基板上的具有与第一晶粒尺寸不同的第二晶粒尺寸的第二多晶硅区域。 此外，还提供了一种制造集成电路的方法。 该方法包括在衬底上形成具有初始晶粒尺寸的第一多晶硅区域。 第一多晶硅区域注入第一导电类型的第一掺杂剂和第二掺杂剂。 在注入之后，第一多晶硅区域具有比初始晶粒尺寸大的第一晶粒尺寸。 然后，对第一多晶硅区域进行激光快速热退火处理。

公开(公告)号：US20150244401A1

公开(公告)日：2015-08-27

申请号：US14617938

申请日：2015-02-10

Applicant: Mediatek Inc.

Inventor： Yuan-Hung Chung ,  Meng-Hsiung Hung ,  Chun-Wei Lin ,  Wei-Kai Hong ,  Keng Leong Fong ,  George Chien ,  Ming-Yeh Hsu

IPC: H04B1/02 ,  H04W4/00 ,  H03F1/02 ,  H03F3/189 ,  H03F3/20

CPC classification number: H04W4/80 ,  H03F1/565 ,  H03F3/19 ,  H03F3/24 ,  H03F3/245 ,  H03F2200/09 ,  H03F2200/222 ,  H03F2200/336 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/541 ,  H04B1/0458 ,  H04B2001/0408 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/26 ,  Y02D70/40

Abstract: A transmitting device includes a transmitting chain, a configurable power amplifier device and an impedance tuning circuit. The transmitting chain is arranged to generate a radio frequency signal. The configurable power amplifier device is arranged to support at least a first power amplifier configuration and a second power amplifier configuration, wherein the configurable power amplifier device employs the first power amplifier configuration to receive and amplify the radio frequency signal when the transmitting device is operated in a first operation mode, and employs the second power amplifier configuration to receive and amplify the radio frequency signal when the transmitting device is operated in a second operation mode. The impedance tuning circuit is arranged to adjust an output impedance of the configurable power amplifier device employing the second power amplifier configuration when the transmitting device is operated in the second operation mode.

Abstract translation: 发送装置包括发送链，可配置功率放大器装置和阻抗调谐电路。 发射链被设置成产生射频信号。 配置的功率放大器装置被布置成支持至少第一功率放大器配置和第二功率放大器配置，其中可配置功率放大器设备采用第一功率放大器配置来在发射设备操作时接收和放大射频信号 第一操作模式，并且当发送装置在第二操作模式下操作时采用第二功率放大器配置来接收和放大射频信号。 阻抗调谐电路被布置为当发射装置在第二操作模式下操作时，调整采用第二功率放大器配置的可配置功率放大器装置的输出阻抗。

公开(公告)号：US20140220922A1

公开(公告)日：2014-08-07

申请号：US14258038

申请日：2014-04-22

Applicant: MEDIATEK INC.

Inventor： Yuan-Hung Chung ,  Yi-Shing Shih

IPC: H04B1/12

CPC classification number: H04B1/12 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03F1/26 ,  H03F1/56 ,  H03F3/19 ,  H03F3/45475 ,  H03F2200/294 ,  H04L25/0278

Abstract: A signal processing circuit with noise cancellation includes an impedance matching unit and a transconductance stage. The impedance matching unit is disposed at a first path, and arranged to provide input impedance matching, wherein the impedance matching unit is a passive element, and the first path is coupled between a signal input port and a signal output port. The transconductance stage is disposed at a second path, and arranged to guide circuit introduced noise to the signal output port for noise cancellation at the signal output port, wherein the second path is coupled between the signal input port and the signal output port.

Abstract translation: 具有噪声消除的信号处理电路包括阻抗匹配单元和跨导级。 阻抗匹配单元设置在第一路径处，并且被布置成提供输入阻抗匹配，其中阻抗匹配单元是无源元件，并且第一路径耦合在信号输入端口和信号输出端口之间。 跨导级设置在第二路径处，并且被布置成引导电路引入的噪声到信号输出端口用于信号输出端口处的噪声消除，其中第二路径耦合在信号输入端口和信号输出端口之间。

公开(公告)号：US08750818B2

公开(公告)日：2014-06-10

申请号：US13792224

申请日：2013-03-11

Applicant: Mediatek Inc.

Inventor： Yuan-Hung Chung ,  Yi-Shing Shih

IPC: H04B1/10 ,  H04B1/16

CPC classification number: H04B1/12 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03F1/26 ,  H03F1/56 ,  H03F3/19 ,  H03F3/45475 ,  H03F2200/294 ,  H04L25/0278

Abstract: A signal processing circuit with noise cancellation includes an impedance matching unit and a transconductance stage. The impedance matching unit is disposed at a first path, and arranged to provide input impedance matching, wherein the impedance matching unit is a bilateral element, and the first path is coupled between a signal input port and a signal output port. The transconductance stage is disposed at a second path, and arranged to guide circuit introduced noise to the signal output port for noise cancellation at the signal output port, wherein the second path is coupled between the signal input port and the signal output port.

Abstract translation: 具有噪声消除的信号处理电路包括阻抗匹配单元和跨导级。 阻抗匹配单元设置在第一路径处，并且被布置成提供输入阻抗匹配，其中阻抗匹配单元是双向元件，并且第一路径耦合在信号输入端口和信号输出端口之间。 跨导级设置在第二路径处，并且被布置成引导电路引入的噪声到信号输出端口用于信号输出端口处的噪声消除，其中第二路径耦合在信号输入端口和信号输出端口之间。

公开(公告)号：US09543943B2

公开(公告)日：2017-01-10

申请号：US14468345

申请日：2014-08-26

Applicant: MEDIATEK INC.

Inventor： Yuan-Hung Chung ,  Jiunn-Nan Hwang ,  Yipin Wu ,  Tsung-Ying Tsai ,  Chin-Wei Huang

IPC: H03K5/00 ,  H03K17/687 ,  H03K19/003 ,  H03K17/16 ,  H03H11/04

CPC classification number: H03K17/687 ,  H03H11/0422 ,  H03K17/164 ,  H03K19/00346

Abstract: A digital circuit comprises a plurality of functional circuits and a finite state machine. Each functional circuit comprises a digital macro, a resistance control device and at least one device with capacitance. The digital macro is coupled to a ground. The resistance control device is electrically connected between the digital macro and an always-on power mesh. The at least one device with capacitance is electrically connected between the resistance control device and the ground. The finite state machine is electrically connected to the resistance control device, and is configured to adjust the resistance of the resistance control device.

Abstract translation: 数字电路包括多个功能电路和有限状态机。 每个功能电路包括数字宏，电阻控制装置和至少一个具有电容的装置。 数字宏耦合到地面。 电阻控制装置电连接在数字宏和永久在线功率网之间。 具有电容的至少一个装置电连接在电阻控制装置和地之间。 有限状态机电连接到电阻控制装置，并且被配置为调整电阻控制装置的电阻。