公开(公告)号：US10096543B2

公开(公告)日：2018-10-09

申请号：US14748161

申请日：2015-06-23

Applicant: MEDIATEK INC.

Inventor： Chien-Kai Huang ,  Yuan-Fu Chung ,  Yuan-Hung Chung

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L23/522 ,  H01L49/02

Abstract: The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer and a first dielectric layer. The first metal layer is arranged to be a part of a first electrode of the semiconductor capacitor structure, and the first metal layer comprises a first portion and a second portion. The first portion is formed to have a first pattern, and the second portion is connected to the first portion. The second metal layer is arranged to be a part of a second electrode of the semiconductor capacitor structure, and the first dielectric layer is formed between the first metal layer and the second metal layer.

公开(公告)号：US10236285B2

公开(公告)日：2019-03-19

申请号：US15495185

申请日：2017-04-24

Applicant: MediaTek Inc.

Inventor： Chien-Kai Huang ,  Yuan-Fu Chung ,  Bo-Shih Huang ,  Chang-Tzu Wang

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. The semiconductor device also includes a first doping region formed in a portion of at least one portion of the semiconductor substrate separating the pair of first well regions, and a pair of second doping regions, respectively formed in one of the pair of first well regions, having the first conductivity type. Further, the semiconductor device includes a pair of insulating layers, respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the pair of second doping regions.

公开(公告)号：US09379175B2

公开(公告)日：2016-06-28

申请号：US14557743

申请日：2014-12-02

Applicant: MediaTek Inc.

Inventor： Yuan-Fu Chung ,  Chu-Wei Hu ,  Yuan-Hung Chung

IPC: H01L21/02 ,  H01L49/02 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28 ,  H01L21/324 ,  H01L27/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L21/266 ,  H01L29/167 ,  H01L27/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. Furthermore, a method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.

Abstract translation: 集成电路包括在基板上形成的具有第一晶粒尺寸的第一多晶硅区域。 集成电路还包括形成在基板上的具有与第一晶粒尺寸不同的第二晶粒尺寸的第二多晶硅区域。 此外，还提供了一种制造集成电路的方法。 该方法包括在衬底上形成具有初始晶粒尺寸的第一多晶硅区域。 第一多晶硅区域注入第一导电类型的第一掺杂剂和第二掺杂剂。 在注入之后，第一多晶硅区域具有比初始晶粒尺寸大的第一晶粒尺寸。 然后，对第一多晶硅区域进行激光快速热退火处理。

公开(公告)号：US09793337B2

公开(公告)日：2017-10-17

申请号：US15167783

申请日：2016-05-27

Applicant: MediaTek Inc.

Inventor： Yuan-Fu Chung ,  Chu-Wei Hu ,  Yuan-Hung Chung

IPC: H01L21/70 ,  H01L49/02 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28 ,  H01L21/324 ,  H01L27/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L21/02 ,  H01L21/266 ,  H01L29/167 ,  H01L21/3215 ,  H01L27/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.

公开(公告)号：US09666576B2

公开(公告)日：2017-05-30

申请号：US14884981

申请日：2015-10-16

Applicant: MediaTek Inc.

Inventor： Chien-Kai Huang ,  Yuan-Fu Chung ,  Bo-Shih Huang ,  Chang-Tzu Wang

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0296 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/8611

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the ESD protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type. Moreover, the ESD protection device further includes a pair of second doping regions respectively formed in one of the first well regions, having the first conductivity type, and a pair of insulating layers respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the second doping regions.

公开(公告)号：US09508786B2

公开(公告)日：2016-11-29

申请号：US14886221

申请日：2015-10-19

Applicant: MediaTek Inc.

Inventor： Yuan-Fu Chung ,  Chu-Wei Hu ,  Yuan-Hung Chung

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L49/02 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28 ,  H01L21/324 ,  H01L27/06 ,  H01L21/762 ,  H01L29/06 ,  H01L29/49 ,  H01L21/02 ,  H01L21/266 ,  H01L29/167 ,  H01L27/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: A method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.

Abstract translation: 还提供了一种制造集成电路的方法。 该方法包括在衬底上形成具有初始晶粒尺寸的第一多晶硅区域。 第一多晶硅区域注入第一导电类型的第一掺杂剂和第二掺杂剂。 在注入之后，第一多晶硅区域具有比初始晶粒尺寸大的第一晶粒尺寸。 然后，对第一多晶硅区域进行激光快速热退火处理。

公开(公告)号：US20160049462A1

公开(公告)日：2016-02-18

申请号：US14748161

申请日：2015-06-23

Applicant: Mediatek Inc.

Inventor： Chien-Kai Huang ,  Yuan-Fu Chung ,  Yuan-Hung Chung

IPC: H01L49/02

CPC classification number: H01L28/86 ,  H01L23/5223 ,  H01L28/60 ,  H01L28/88 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer and a first dielectric layer. The first metal layer is arranged to be a part of a first electrode of the semiconductor capacitor structure, and the first metal layer comprises a first portion and a second portion. The first portion is formed to have a first pattern, and the second portion is connected to the first portion. The second metal layer is arranged to be a part of a second electrode of the semiconductor capacitor structure, and the first dielectric layer is formed between the first metal layer and the second metal layer.

Abstract translation: 本发明提供一种半导体电容器结构。 半导体电容器结构包括第一金属层，第二金属层和第一介电层。 第一金属层被布置为半导体电容器结构的第一电极的一部分，并且第一金属层包括第一部分和第二部分。 第一部分形成为具有第一图案，并且第二部分连接到第一部分。 第二金属层被布置为半导体电容器结构的第二电极的一部分，并且第一介电层形成在第一金属层和第二金属层之间。