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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09543377B2

    公开(公告)日：2017-01-10

    申请号：US14548298

    申请日：2014-11-20

    Applicant: MEDIATEK INC.

    Inventor： Bo-Shih Huang ,  Chien-Hui Chuang ,  Cheng-Chou Hung

    IPC: H01L27/06 ,  H01L29/73 ,  H01L29/78 ,  H01L23/60 ,  H01L29/788 ,  H01L29/06 ,  H01L29/74 ,  H01L29/45

    CPC classification number: H01L29/0603 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/45 ,  H01L29/7436

    Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

    Abstract translation: 公开了一种包括衬底的半导体器件。 基材包括：一类的孔; 设置在类型1的阱中的类型2的第一掺杂区域; 一类二井，毗邻一井; 以及掺杂在类型2的阱中的第一掺杂区域。 衬底不包括设置在由第二类型的第一掺杂区，类型二的阱，类型二的阱和类型1的第一掺杂区形成的电流路径中的隔离材料。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160148992A1

    公开(公告)日：2016-05-26

    申请号：US14548298

    申请日：2014-11-20

    Applicant: MEDIATEK INC.

    Inventor： Bo-Shih Huang ,  Chien-Hui Chuang ,  Cheng-Chou Hung

    IPC: H01L29/06 ,  H01L29/45

    CPC classification number: H01L29/0603 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/45 ,  H01L29/7436

    Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

    Abstract translation: 公开了一种包括衬底的半导体器件。 基材包括：一类的孔; 设置在类型1的阱中的类型2的第一掺杂区域; 一类二井，毗邻一井; 以及掺杂在类型2的阱中的第一掺杂区域。 衬底不包括设置在由第二类型的第一掺杂区，类型二的阱，类型二的阱和类型1的第一掺杂区形成的电流路径中的隔离材料。

    ESD PROTECTION CIRCUIT FOR NEGATIVE VOLTAGE OPERATION
    3.
    发明公开
    ESD PROTECTION CIRCUIT FOR NEGATIVE VOLTAGE OPERATION 审中-公开

    公开(公告)号：US20240153945A1

    公开(公告)日：2024-05-09

    申请号：US18373288

    申请日：2023-09-27

    Applicant: MEDIATEK INC.

    Inventor： Ming-Chun Chen ,  Bo-Shih Huang

    IPC: H01L27/02

    CPC classification number: H01L27/0262

    Abstract: The present invention provides a chip including an I/O pin and an ESD protection circuit. The ESD protection circuit includes a P-type device and a first diode, wherein the P-type device is coupled between the I/O pin and a ground voltage, and an anode of the first diode is directly connected to the I/O pin. In addition, the ESD protection circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin.

    ESD protecting circuit
    5.
    发明授权
    ESD protecting circuit 有权

    公开(公告)号：US09679884B2

    公开(公告)日：2017-06-13

    申请号：US14936685

    申请日：2015-11-10

    Applicant: MEDIATEK INC.

    Inventor： Bo-Shih Huang

    IPC: H02H9/04 ,  H01L27/02

    CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H02H9/046

    Abstract: An ESD protecting circuit comprising: a first and a second voltage pad; an I/O pad; a first ESD protecting module, comprising a first terminal coupled to the first voltage pad, and comprising a second terminal; a switch, comprising a first terminal coupled to the second terminal of the first ESD protecting module, comprising a second terminal coupled to the I/O pad, and comprising a control terminal for receiving a control signal; a second ESD protecting module, comprising a first terminal coupled to the first terminal of the MOS transistor, and comprising a second terminal coupled to the second voltage pad; and an ESD detecting circuit, for detecting if an ESD voltage exists, for generating the control signal to control the MOS transistor to be conductive when an ESD voltage is detected and to control the MOS transistor to be nonconductive when the ESD voltage is not detected.

    Electrostatic discharge (ESD) protection device
    6.
    发明授权
    Electrostatic discharge (ESD) protection device 有权

    公开(公告)号：US09666576B2

    公开(公告)日：2017-05-30

    申请号：US14884981

    申请日：2015-10-16

    Applicant: MediaTek Inc.

    Inventor： Chien-Kai Huang ,  Yuan-Fu Chung ,  Bo-Shih Huang ,  Chang-Tzu Wang

    IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

    CPC classification number: H01L27/0255 ,  H01L27/0296 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/8611

    Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the ESD protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type. Moreover, the ESD protection device further includes a pair of second doping regions respectively formed in one of the first well regions, having the first conductivity type, and a pair of insulating layers respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the second doping regions.

    Fin field-effect transistor gated diode
    7.
    发明授权
    Fin field-effect transistor gated diode 有权

    公开(公告)号：US09947659B2

    公开(公告)日：2018-04-17

    申请号：US15122379

    申请日：2015-05-25

    Applicant: MediaTek Inc.

    Inventor： Chang-Tzu Wang ,  Bo-Shih Huang

    IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L23/535

    CPC classification number: H01L27/0886 ,  H01L23/535 ,  H01L27/027 ,  H01L29/785

    Abstract: The invention provides a semiconductor device. The semiconductor device includes a fin field effect transistor (finFET) array including finFET units. Each of the finFET units includes a substrate having a fin along a first direction. A first metal strip pattern and a second metal strip pattern are formed on the fin, extending along a second direction that is different from the first direction. The first and second metal strip patterns are conformally formed on opposite sidewalls and a top surface of the fin, respectively. A first contact and a second contact are formed on the fin. The first and second metal strip patterns are disposed between the first and second contacts. A first dummy contact is formed on the fin, sandwiched between the first and second metal strip patterns.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20170084685A1

    公开(公告)日：2017-03-23

    申请号：US15367126

    申请日：2016-12-01

    Applicant: MEDIATEK INC.

    Inventor： Bo-Shih Huang ,  Chien-Hui Chuang ,  Cheng-Chou Hung

    IPC: H01L29/06 ,  H01L29/36 ,  H01L29/45

    CPC classification number: H01L29/0603 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/45 ,  H01L29/7436

    Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

    ESD protecting circuit
    10.
    发明授权
    ESD protecting circuit 有权
    ESD保护电路

    公开(公告)号：US09214806B1

    公开(公告)日：2015-12-15

    申请号：US14451434

    申请日：2014-08-05

    Applicant: MEDIATEK INC.

    Inventor： Bo-Shih Huang

    IPC: H01L23/62 ,  H02H9/04 ,  H01L27/02

    CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H02H9/046

    Abstract: An ESD protecting circuit, which comprises: a first voltage pad; a second voltage pad; an I/O pad; a first ESD protecting module, comprising a first terminal coupled to the first voltage pad; a MOS transistor, comprising a first terminal coupled to a second terminal of the first ESD protecting module, comprising a second terminal coupled to the I/O pad, and comprising a control terminal for receiving a control signal; a second ESD protecting module, comprising a first terminal coupled to the first terminal of the MOS transistor, and comprising a second terminal coupled to the second voltage pad; and an ESD detecting circuit, for generating the control signal to control the MOS transistor to be conductive when an ESD voltage is detected and to control the MOS transistor to be nonconductive when the ESD voltage is not detected.

    Abstract translation: 一种ESD保护电路，包括：第一电压焊盘; 第二电压垫; 一个I / O焊盘; 第一ESD保护模块，包括耦合到所述第一电压焊盘的第一端子; MOS晶体管，包括耦合到第一ESD保护模块的第二端子的第一端子，包括耦合到I / O焊盘的第二端子，并且包括用于接收控制信号的控制端子; 第二ESD保护模块，包括耦合到所述MOS晶体管的所述第一端子的第一端子，并且包括耦合到所述第二电压焊盘的第二端子; 以及ESD检测电路，用于在检测到ESD电压时产生用于控制MOS晶体管导通的控制信号，并且在未检测到ESD电压时控制MOS晶体管为非导通。

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