公开(公告)号：US20180025985A1

公开(公告)日：2018-01-25

申请号：US15498542

申请日：2017-04-27

Applicant: MEDIATEK INC.

Inventor： Min-Chen LIN ,  Che-Ya CHOU ,  Nan-Cheng CHEN

IPC: H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L23/3185 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L24/20 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16195 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2924/37001

Abstract: A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.

公开(公告)号：US20150342038A1

公开(公告)日：2015-11-26

申请号：US14816204

申请日：2015-08-03

Applicant: MediaTek Inc.

Inventor： Sheng-Ming CHANG ,  Shih-Chieh LIN ,  Nan-Cheng CHEN

IPC: H05K1/02

CPC classification number: H05K1/0219 ,  H05K1/0218 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/114 ,  H05K1/115 ,  H05K2201/0723 ,  H05K2201/09672 ,  H05K2201/09709 ,  H05K2201/10522 ,  H05K2201/10674

Abstract: A printed circuit board for mobile platforms includes a core substrate having a first side, a ground plane covering on the first side, a first insulating layer covering the ground plane, and a plurality of first signal traces and a plurality of first ground traces, alternatively arranged on the first insulating layer, a second insulating layer connecting to the first insulating layer, and a plurality of second signal traces separated from each other, disposed on the second insulating layer, wherein the second signal traces are disposed directly on spaces between the first signal traces and the first ground traces adjacent thereto, wherein coverage of the ground plane is corresponding to disposition of the first signal trace, the first ground trace, the second signal trace and the second ground trace.

Abstract translation: 一种用于移动平台的印刷电路板包括具有第一侧的芯基板，覆盖在第一侧的接地平面，覆盖接地平面的第一绝缘层，以及多个第一信号迹线和多个第一接地迹线， 布置在第一绝缘层上，连接到第一绝缘层的第二绝缘层和彼此分离的多个第二信号迹线，设置在第二绝缘层上，其中第二信号迹线直接设置在第一绝缘层之间的空间上 信号迹线和与其相邻的第一接地迹线，其中接地平面的覆盖对应于第一信号迹线，第一接地迹线，第二信号迹线和第二接地迹线的布置。

公开(公告)号：US20130277801A1

公开(公告)日：2013-10-24

申请号：US13790097

申请日：2013-03-08

Applicant: MEDIATEK INC.

Inventor： Nan-Cheng CHEN ,  Tung-Hsien HSIEH

IPC: H01L23/522

CPC classification number: H01L23/5223 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L25/105 ,  H01L27/0248 ,  H01L27/1255 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a lower chip package; an upper chip package disposed on an upper surface of the lower chip package; at least one conducting element disposed between the lower chip package and the upper chip package; and at least one decoupling capacitor disposed on the upper surface of the lower chip package, wherein the decoupling capacitor is not covered by the upper chip package, and the decoupling capacitor is electrically connected to a power line or a ground line in the lower chip package.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括：一个较低的芯片封装; 上芯片封装，设置在下芯片封装的上表面上; 设置在下芯片封装和上芯片封装之间的至少一个导电元件; 以及设置在下芯片封装的上表面上的至少一个去耦电容器，其中去耦电容器不被上芯片封装覆盖，并且去耦电容器电连接到下芯片封装中的电源线或接地线 。

公开(公告)号：US20150379184A1

公开(公告)日：2015-12-31

申请号：US14843094

申请日：2015-09-02

Applicant: MediaTek Inc

Inventor： Fu-Kang PAN ,  Nan-Cheng CHEN ,  Shih-Chieh LIN ,  HUI-CHI TANG ,  Ying LIU ,  Yang LIU ,  Ching-Chih Li

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/38 ,  G06F2217/40

Abstract: A printed circuit board (PCB) is provided. The PCB has a specific routing module, having a first chip, a memory chip, and a plurality of traces designed for interconnection between the first chip and the memory chip according to a routing configuration between the first chip and the memory chip. The memory chip is a dynamic random access memory (DRAM) with a memory type, the specific routing module is obtained from a module group comprising a plurality of routing modules according to a plurality of PCB parameters, and module group is obtained from a database according to the memory type of the DRAM.

Abstract translation: 提供印刷电路板（PCB）。 PCB具有特定的路由模块，具有根据第一芯片和存储芯片之间的布线配置的第一芯片，存储器芯片和设计用于第一芯片和存储器芯片之间的互连的多条迹线。 存储器芯片是具有存储器类型的动态随机存取存储器（DRAM），根据多个PCB参数从包括多个路由模块的模块组获得特定路由模块，并且从数据库获得模块组 到DRAM的存储器类型。

公开(公告)号：US20150379180A1

公开(公告)日：2015-12-31

申请号：US14843113

申请日：2015-09-02

Applicant: MediaTek Inc

Inventor： Fu-Kang PAN ,  Nan-Cheng CHEN ,  Shih-Chieh LIN ,  HUI-CHI TANG ,  Ying LIU ,  Yang LIU ,  Ching-Chih Li

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/38 ,  G06F2217/40

Abstract: A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

Abstract translation: 提供了印刷电路板（PCB）的布局方法。 该方法获得要安装在PCB上的动态随机存取存储器（DRAM）的存储器类型，根据DRAM的存储器类型从数据库获取模块组，其中模块组包括多个路由模块，获得 多个PCB参数，根据PCB参数从模块组中选择特定的路由模块，并将特定路由模块实现为PCB制造的布局设计。 特定路由模块包括关于主芯片，存储芯片和主芯片与存储芯片之间的布线配置的布局信息。

公开(公告)号：US20190051609A1

公开(公告)日：2019-02-14

申请号：US16163614

申请日：2018-10-18

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung HSU ,  Tao CHENG ,  Nan-Cheng CHEN ,  Che-Ya CHOU ,  Wen-Chou WU ,  Yen-Ju LU ,  Chih-Ming HUNG ,  Wei-Hsiu HSU

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US20140264812A1

公开(公告)日：2014-09-18

申请号：US14188881

申请日：2014-02-25

Applicant: MediaTek Inc.

Inventor： Sheng-Ming CHANG ,  Tung-Hsien HSIEH ,  Nan-Cheng CHEN

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15183 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一半导体封装。 第一半导体封装包括具有第一器件附着表面和与第一器件附着表面相对的第一凸起附着表面的第一本体。 第二半导体封装被结合到第一半导体封装的第一器件附着表面。 第二包装包括具有第二装置附着表面的第二主体和与第二装置附接表面相对的第二凸起附着表面。 动态随机存取存储器（DRAM）装置安装在第二装置附接表面上。 去耦电容器安装在第二器件附着表面上。 导电结构设置在第二封装的第二凸起附接表面上，连接到第一半导体封装的第一主体的第一凸起附着表面。

公开(公告)号：US20200381365A1

公开(公告)日：2020-12-03

申请号：US16994764

申请日：2020-08-17

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung HSU ,  Tao CHENG ,  Nan-Cheng CHEN ,  Che-Ya CHOU ,  Wen-Chou WU ,  Yen-Ju LU ,  Chih-Ming HUNG ,  Wei-Hsiu HSU

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065 ,  H01L25/16 ,  H01L23/50 ,  H01L23/498 ,  H01L21/683 ,  H01Q9/04 ,  H01L23/66 ,  H01Q1/22

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US20180082936A1

公开(公告)日：2018-03-22

申请号：US15700220

申请日：2017-09-11

Applicant: MEDIATEK INC.

Inventor： Shih-Yi SYU ,  Chia-Yu JIN ,  Che-Ya CHOU ,  Wen-Sung HSU ,  Nan-Cheng CHEN

IPC: H01L23/498 ,  H01L23/42 ,  H01L23/64 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/164 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.

公开(公告)号：US20160358877A1

公开(公告)日：2016-12-08

申请号：US15238454

申请日：2016-08-16

Applicant: MediaTek Inc.

Inventor： Che-Ya CHOU ,  Wen-Sung HSU ,  Nan-Cheng CHEN

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/16 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/12042 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.

Abstract translation: 提供半导体封装。 半导体封装包括通过第一导电结构结合到基底的半导体器件。 半导体器件包括包括导电迹线的载体衬底。 导电迹线的一部分是细长的。 半导体器件还包括载体衬底上方的第二导电结构。 第二导电结构的一部分与导电迹线的部分接触。 半导体器件还包括安装在导电迹线上方的半导体本体。 半导体本体连接到第二导电结构。