公开(公告)号：US20180082936A1

公开(公告)日：2018-03-22

申请号：US15700220

申请日：2017-09-11

Applicant: MEDIATEK INC.

Inventor： Shih-Yi SYU ,  Chia-Yu JIN ,  Che-Ya CHOU ,  Wen-Sung HSU ,  Nan-Cheng CHEN

IPC: H01L23/498 ,  H01L23/42 ,  H01L23/64 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/164 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.

公开(公告)号：US20240371781A1

公开(公告)日：2024-11-07

申请号：US18654239

申请日：2024-05-03

Applicant: MEDIATEK INC.

Inventor： Shu-Yuan TSENG ,  Sheng-Yuan FU ,  Duen-Yi HO ,  Chia-Yu JIN

IPC: H01L23/538 ,  H01L25/065

Abstract: An electronic device used in the Universal Chiplet Interconnect Express (UCIe) standard is provided. The electronic device includes a substrate and first and second semiconductor devices. The first and second semiconductor devices are disposed on a top surface of the substrate. The substrate includes an interconnect structure electrically connected between the first and second semiconductor devices. The interconnect structure includes a first pad, a first signal trace and first and second via structures. The first pad is located on the top surface of the substrate. The first signal trace is covered by the first and second semiconductor devices. The first via structure is electrically connected between the first pad and the first signal trace. The second via structure is electrically connected between the first via structure and the first signal trace. The first via structure is misaligned with the second via structure.