公开(公告)号：US09490241B2

公开(公告)日：2016-11-08

申请号：US13533113

申请日：2012-06-26

Applicant: Masumi Nomura ,  Tatsuji Nishijima ,  Kosei Noda

Inventor： Masumi Nomura ,  Tatsuji Nishijima ,  Kosei Noda

IPC: H01L29/10 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L27/0207 ,  H01L27/1108

Abstract: A semiconductor device which is downsized while a short-channel effect is suppressed and whose power consumption is reduced is provided. A downsized SRAM circuit is formed, which includes a first inverter including a first transistor and a second transistor overlapping with each other; a second inverter including a third transistor and a fourth transistor overlapping with each other; a first selection transistor; and a second selection transistor. An output terminal of the first inverter, an input terminal of the second inverter, and one of a source and a drain of the first selection transistor are connected to one another, and an output terminal of the second inverter, an input terminal of the first inverter, and one of a source and a drain of the second selection transistor are connected to one another.

Abstract translation: 提供了在抑制短通道效应并且其功耗降低的同时小型化的半导体器件。 形成了小型SRAM电路，其包括第一反相器，其包括彼此重叠的第一晶体管和第二晶体管; 第二反相器，包括彼此重叠的第三晶体管和第四晶体管; 第一选择晶体管; 和第二选择晶体管。 第一反相器的输出端子，第二反相器的输入端子和第一选择晶体管的源极和漏极之一彼此连接，第二反相器的输出端子，第一反相器的输入端子，第一反相器的输入端子， 反相器和第二选择晶体管的源极和漏极之一彼此连接。

公开(公告)号：US08643007B2

公开(公告)日：2014-02-04

申请号：US13397838

申请日：2012-02-16

Applicant: Masumi Nomura ,  Kosei Noda

Inventor： Masumi Nomura ,  Kosei Noda

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/42384 ,  H01L29/78624

Abstract: It is an object to reduce concentration of an electric field on an end of a drain electrode of a semiconductor device. A semiconductor device includes an oxide semiconductor film including a first region and a second region; a pair of electrodes which is partly in contact with the oxide semiconductor film; a gate insulating film over the oxide semiconductor film; and a gate electrode that overlaps with part of one of the pair of electrodes and the first region with the gate insulating film provided therebetween. At least part of the first region and part of the second region are between the pair of electrodes. The gate electrode does not overlap with the other of the pair of electrodes.

Abstract translation: 本发明的目的是减少半导体器件的漏电极端部的电场浓度。 半导体器件包括包括第一区域和第二区域的氧化物半导体膜; 一部分与氧化物半导体膜接触的电极; 氧化物半导体膜上的栅极绝缘膜; 以及栅极电极，其与所述一对电极中的一个电极的一部分和所述第一区域重叠，并且所述栅极绝缘膜设置在所述第一区域之间。 第一区域的至少一部分和第二区域的一部分位于该对电极之间。 栅极电极不与另一对电极重叠。

公开(公告)号：US09799461B2

公开(公告)日：2017-10-24

申请号：US13596189

申请日：2012-08-28

Applicant: Kosei Noda ,  Kazutaka Kuriki ,  Nobuhiro Inoue

Inventor： Kosei Noda ,  Kazutaka Kuriki ,  Nobuhiro Inoue

IPC: H01M4/38 ,  H01M4/48 ,  H01G11/68 ,  H01G11/06 ,  H01G11/28 ,  H01G11/30 ,  H01G11/46 ,  H01G11/86 ,  H01M4/131 ,  H01M4/134 ,  H01M4/1391 ,  H01M4/1395 ,  H01M4/36 ,  H01M10/052

CPC classification number: H01G11/68 ,  H01G11/06 ,  H01G11/28 ,  H01G11/30 ,  H01G11/46 ,  H01G11/86 ,  H01M4/131 ,  H01M4/134 ,  H01M4/1391 ,  H01M4/1395 ,  H01M4/366 ,  H01M4/386 ,  H01M4/387 ,  H01M4/48 ,  H01M4/483 ,  H01M10/052 ,  Y02E60/13 ,  Y02T10/7011 ,  Y02T10/7022

Abstract: As an electrode for a power storage device, an electrode including a current collector, a first active material layer over the current collector, and a second active material layer that is over the first active material layer and includes a particle containing niobium oxide and a granular active material is used, whereby the charge-discharge cycle characteristics and rate characteristics of the power storage device can be improved. Moreover, contact between the granular active material and the particle containing niobium oxide makes the granular active material physically fixed; accordingly, deterioration due to expansion and contraction of the active material which occur along with charge and discharge of the power storage device, such as powdering of the active material or its separation from the current collector, can be suppressed.

公开(公告)号：US09425045B2

公开(公告)日：2016-08-23

申请号：US13107283

申请日：2011-05-13

Applicant: Shunpei Yamazaki ,  Toshinari Sasaki ,  Kosei Noda

Inventor： Shunpei Yamazaki ,  Toshinari Sasaki ,  Kosei Noda

IPC: H01L21/02 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/385 ,  H01L27/1225 ,  H01L29/7869

Abstract: It is an object to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. An oxide semiconductor film serving as a channel formation region of a transistor is formed by a sputtering method at a temperature higher than 200° C., so that the number of water molecules eliminated from the oxide semiconductor film can be 0.5/nm3 or less according to thermal desorption spectroscopy. A substance including a hydrogen atom such as hydrogen, water, a hydroxyl group, or hydride which causes variation in the electric characteristics of a transistor including an oxide semiconductor is prevented from entering the oxide semiconductor film, whereby the oxide semiconductor film can be highly purified and made to be an electrically i-type (intrinsic) semiconductor.

Abstract translation: 本发明的目的是提供一种具有稳定的电特性和高可靠性的氧化物半导体的半导体装置。 通过溅射法在高于200℃的温度下形成用作晶体管的沟道形成区的氧化物半导体膜，从氧化物半导体膜中除去的水分子数可以为0.5nm / nm 3以下 到热解吸光谱。 包含氢原子的物质，例如氢，水，羟基或氢化物，其导致包括氧化物半导体的晶体管的电特性发生变化，从而防止氧化物半导体膜进入氧化物半导体膜，由此氧化物半导体膜可以被高度纯化 并制成电i型（本征）半导体。

公开(公告)号：US08900916B2

公开(公告)日：2014-12-02

申请号：US12832329

申请日：2010-07-08

Applicant: Shunpei Yamazaki ,  Miyuki Hosoba ,  Kosei Noda ,  Hiroki Ohara ,  Toshinari Sasaki ,  Junichiro Sakata

Inventor： Shunpei Yamazaki ,  Miyuki Hosoba ,  Kosei Noda ,  Hiroki Ohara ,  Toshinari Sasaki ,  Junichiro Sakata

IPC: H01L21/00

CPC classification number: H01L29/66969 ,  H01L21/477 ,  H01L27/1225 ,  H01L29/7869

Abstract: A highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics, and a manufacturing method thereof. In the manufacturing method of the semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region is an oxide semiconductor layer, heat treatment which reduces impurities such as moisture to improve the purity of the oxide semiconductor layer and oxidize the oxide semiconductor layer (heat treatment for dehydration or dehydrogenation) is performed. Not only impurities such as moisture in the oxide semiconductor layer but also those existing in a gate insulating layer are reduced, and impurities such as moisture existing in interfaces between the oxide semiconductor layer and films provided over and under and in contact with the oxide semiconductor layer are reduced.

Abstract translation: 一种高度可靠的半导体器件及其制造方法，其包括具有稳定电特性的薄膜晶体管。 在包括具有沟道形成区域的半导体层是氧化物半导体层的薄膜晶体管的半导体器件的制造方法中，减少诸如水分的杂质的热处理以提高氧化物半导体层的纯度并氧化氧化物 进行半导体层（脱水或脱氢的热处理）。 氧化物半导体层中的水分等杂质，以及存在于栅极绝缘层中的杂质都会降低，氧化物半导体层和氧化物半导体层之间的界面中存在的水分等杂质与氧化物半导体层 减少了

公开(公告)号：US08803142B2

公开(公告)日：2014-08-12

申请号：US12907722

申请日：2010-10-19

Applicant: Shunpei Yamazaki ,  Masashi Tsubuku ,  Kosei Noda ,  Kouhei Toyotaka ,  Kazunori Watanabe ,  Hikaru Harada

Inventor： Shunpei Yamazaki ,  Masashi Tsubuku ,  Kosei Noda ,  Kouhei Toyotaka ,  Kazunori Watanabe ,  Hikaru Harada

IPC: H01L29/04 ,  H01L29/12 ,  H01L29/78

CPC classification number: H01L29/7869 ,  G06F15/76 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1112 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78696

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Abstract translation: 目的是提供一种存储器件，其包括可通过具有低截止电流的薄膜晶体管无故障地操作的存储元件。 提供了一种存储器件，其中包括至少一个包括氧化物半导体层的薄膜晶体管的存储元件被布置为矩阵。 包括氧化物半导体层的薄膜晶体管具有高场效应迁移率和低截止电流，因此可以有利地操作而没有问题。 此外，可以降低功耗。 由于存储器件和像素可以形成在一个衬底上，所以这种存储器件在包括氧化物半导体层的薄膜晶体管被设置在显示器件的像素中的情况下是特别有效的。

公开(公告)号：US08772849B2

公开(公告)日：2014-07-08

申请号：US13410608

申请日：2012-03-02

Applicant: Kosei Noda

Inventor： Kosei Noda

IPC: H01L29/76 ,  H01L29/12

CPC classification number: H01L27/1156 ,  G11C16/0433 ,  H01L28/40

Abstract: A semiconductor memory device includes a semiconductor film; a first gate insulating film covering the semiconductor film; a first gate electrode provided over the semiconductor film with the first gate insulating film interposed therebetween; a first conductive film which is provided over the first gate insulating film; an insulating film which is provided over the first gate insulating film, exposes top surfaces of the first gate electrode and the first conductive film, and has a groove portion between the first gate electrode and the first conductive film; an oxide semiconductor film which is provided over the insulating film and is in contact with the first gate electrode, the first conductive film, and the groove portion; a second gate insulating film covering the oxide semiconductor film; and a second gate electrode provided over the oxide semiconductor film and the groove portion with the second gate insulating film interposed therebetween.

Abstract translation: 半导体存储器件包括半导体膜; 覆盖半导体膜的第一栅极绝缘膜; 设置在所述半导体膜上的第一栅电极，其间插入有所述第一栅极绝缘膜; 设置在所述第一栅极绝缘膜上的第一导电膜; 设置在第一栅极绝缘膜上的绝缘膜暴露第一栅电极和第一导电膜的顶表面，并且在第一栅电极和第一导电膜之间具有沟槽部分; 氧化物半导体膜，设置在所述绝缘膜上并且与所述第一栅电极，所述第一导电膜和所述槽部接触; 覆盖氧化物半导体膜的第二栅极绝缘膜; 以及设置在所述氧化物半导体膜和所述沟槽部分上方的第二栅电极，其间插入有所述第二栅极绝缘膜。

公开(公告)号：US08525304B2

公开(公告)日：2013-09-03

申请号：US13110240

申请日：2011-05-18

Applicant: Yuta Endo ,  Toshinari Sasaki ,  Kosei Noda ,  Mizuho Sato

Inventor： Yuta Endo ,  Toshinari Sasaki ,  Kosei Noda ,  Mizuho Sato

IPC: H01L23/58

CPC classification number: H01L21/02554 ,  H01L21/02488 ,  H01L21/02664 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

公开(公告)号：US08426231B2

公开(公告)日：2013-04-23

申请号：US12857820

申请日：2010-08-17

Applicant: Atsuo Isobe ,  Noriko Harima ,  Noriko Matsumoto ,  Akihisa Shimomura ,  Kosei Noda ,  Kazuko Yamawaki ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Takashi Hamada

Inventor： Atsuo Isobe ,  Noriko Harima ,  Noriko Matsumoto ,  Akihisa Shimomura ,  Kosei Noda ,  Kazuko Yamawaki ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Takashi Hamada

IPC: H01L31/18

CPC classification number: H01L31/103 ,  H01L27/14643 ,  H01L31/105 ,  H01L31/1804 ,  H01L31/1864 ,  H01L31/1892 ,  Y02E10/547 ,  Y02P70/521

Abstract: An object of an embodiment of the disclosed invention is to provide a semiconductor device including a photoelectric conversion element with excellent characteristics. An object of an embodiment of the disclosed invention is to provide a semiconductor device including a photoelectric conversion device with excellent characteristic through a simple process. A semiconductor device is provided, which includes a light-transmitting substrate; an insulating layer over the light-transmitting substrate; and a photoelectric conversion element over the insulating layer. The photoelectric conversion element includes a single crystal semiconductor layer including a semiconductor region having an effect of photoelectric conversion, a semiconductor region having a first conductivity type, and a semiconductor region having a second conductivity type; a first electrode electrically connected to the semiconductor region having the first conductivity type; and a second electrode electrically connected to the semiconductor region having the second conductivity type.

Abstract translation: 所公开的发明的一个实施例的目的是提供一种包括具有优异特性的光电转换元件的半导体器件。 所公开的发明的一个实施例的目的是提供一种包括通过简单工艺具有优异特性的光电转换装置的半导体器件。 提供了一种半导体器件，其包括透光衬底; 透光基板上的绝缘层; 和绝缘层上的光电转换元件。 光电转换元件包括具有具有光电转换效果的半导体区域，具有第一导电类型的半导体区域和具有第二导电类型的半导体区域的单晶半导体层; 电连接到具有第一导电类型的半导体区域的第一电极; 以及电连接到具有第二导电类型的半导体区域的第二电极。

公开(公告)号：US08421069B2

公开(公告)日：2013-04-16

申请号：US12904579

申请日：2010-10-14

Applicant: Shunpei Yamazaki ,  Jun Koyama ,  Hiroyuki Miyake ,  Kei Takahashi ,  Kouhei Toyotaka ,  Masashi Tsubuku ,  Kosei Noda ,  Hideaki Kuwabara

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Hiroyuki Miyake ,  Kei Takahashi ,  Kouhei Toyotaka ,  Masashi Tsubuku ,  Kosei Noda ,  Hideaki Kuwabara

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/04 ,  H01L31/00 ,  H01L27/15 ,  H01L29/26 ,  H01L31/12 ,  H01L33/00

CPC classification number: H01L29/7869 ,  H01L21/84 ,  H01L23/552 ,  H01L23/60 ,  H01L23/66 ,  H01L25/16 ,  H01L27/0222 ,  H01L27/10873 ,  H01L27/12 ,  H01L27/1225 ,  H01L28/20 ,  H01L28/60 ,  H01L29/78609 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.

Abstract translation: 目的是减少用于LSI，CPU或存储器的晶体管的漏电流和寄生电容。 包括在LSI，CPU或存储器中的半导体集成电路使用使用氧化物半导体形成的晶体管来制造，所述氧化物半导体是通过从作为电子给体（供体）中除去作为电子给体（供体）的杂质而获得的内在或本质上的半导体 氧化物半导体，并且具有比硅半导体更大的能隙，并且形成在半导体衬底上。 通过形成在半导体衬底上的晶体管，并且包括具有充分降低的氢浓度的高度净化的氧化物半导体层，可以实现其由漏电流引起的功率消耗低的半导体器件。