知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.013 seconds)

    Wafer-level chip-size package with redistribution layer
    1.
    发明授权
    Wafer-level chip-size package with redistribution layer 有权

    公开(公告)号：US10998267B2

    公开(公告)日：2021-05-04

    申请号：US15286844

    申请日：2016-10-06

    Applicant: MediaTek Inc.

    Inventor： Yan-Liang Ji ,  Ming-Jen Hsiung

    IPC: H01L23/528 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31

    Abstract: A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer.

    Semiconductor device capable of high-voltage operation
    4.
    发明授权
    Semiconductor device capable of high-voltage operation 有权

    公开(公告)号：US10541328B2

    公开(公告)日：2020-01-21

    申请号：US16225077

    申请日：2018-12-19

    Applicant: MEDIATEK INC.

    Inventor： Cheng-Hua Lin ,  Yan-Liang Ji ,  Chih-Wen Hsiung

    IPC: H01L29/00 ,  H01L29/78 ,  H01L29/40 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.

    ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF
    5.
    发明申请
    ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF 审中-公开
    电子元器件及其制造方法

    公开(公告)号：US20170047398A1

    公开(公告)日：2017-02-16

    申请号：US15206399

    申请日：2016-07-11

    Applicant: MEDIATEK Inc.

    Inventor： Yan-Liang Ji ,  Cheng-Hua Lin ,  Puo-Yu Chiang

    IPC: H01L29/06 ,  H01L21/768 ,  H01L29/423 ,  H01L29/36 ,  H01L23/535

    CPC classification number: H01L29/0653 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/36 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42356 ,  H01L29/7835

    Abstract: The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface. first doped region embedded in the semiconductor substrate. The second doped region is embedded in the semiconductor substrate. The gate structure is formed on the upper surface. The dielectric layer is formed above the upper surface and located between the first doped region and the second doped region. The conductive portion is formed on the dielectric layer.

    Abstract translation: 电子部件包括半导体基板，第一掺杂区域，第二掺杂区域，栅极结构，电介质层和导电部分。 半导体衬底具有上表面。 第一掺杂区域嵌入在半导体衬底中。 第二掺杂区域嵌入在半导体衬底中。 栅极结构形成在上表面上。 电介质层形成在上表面上方并位于第一掺杂区和第二掺杂区之间。 导电部分形成在电介质层上。

    MOS device with isolated drain and method for fabricating the same
    6.
    发明授权
    MOS device with isolated drain and method for fabricating the same 有权
    具有隔离漏极的MOS器件及其制造方法

    公开(公告)号：US09006068B1

    公开(公告)日：2015-04-14

    申请号：US14582626

    申请日：2014-12-24

    Applicant: MediaTek Inc

    Inventor： Puo-Yu Chiang ,  Yan-Liang Ji

    IPC: H01L21/266 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835

    Abstract: A method for fabricating a metal-oxide-semiconductor (MOS) device, performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate; performing a first ion implant process on two portions of the semiconductor substrate exposed by the first patterned mask layer; removing the first patterned mask layer and forming a second patterned mask layer over the semiconductor substrate, exposing a portion of the third well region; performing a second ion implant process to the portion of the third well region exposed by the second patterned mask layer; performing a third implant process to the portion of the third well region exposed by the second patterned mask layer; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.

    Abstract translation: 一种制造金属氧化物半导体（MOS）器件的方法，执行以下操作：形成嵌入在半导体衬底的一部分中的第一阱区; 在所述半导体衬底上形成第一图案化掩模层; 在由第一图案化掩模层曝光的半导体衬底的两个部分上执行第一离子注入工艺; 去除所述第一图案化掩模层并在所述半导体衬底上形成第二图案化掩模层，暴露所述第三阱区域的一部分; 对由第二图案化掩模层暴露的第三阱区的部分执行第二离子注入工艺; 对由第二图案化掩模层暴露的第三阱区的部分执行第三注入工艺; 在所述第三阱区域的一部分中形成源极区域; 以及在所述第五阱区的一部分中形成漏极区。

    Power supplying system with fast charging capability and balanced battery utilization
    8.
    发明公开
    Power supplying system with fast charging capability and balanced battery utilization 审中-公开

    公开(公告)号：US20230261484A1

    公开(公告)日：2023-08-17

    申请号：US18096023

    申请日：2023-01-12

    Applicant: MEDIATEK INC.

    Inventor： Yan-Liang Ji

    IPC: H02J7/00

    CPC classification number: H02J7/0024 ,  H02J7/0063

    Abstract: A power supplying system for supplying power in an electronic device includes rechargeable batteries coupled to a functional block of the electronic device. The rechargeable batteries include a first battery and a second battery. In a normal mode, the first battery and the second battery are connected in parallel between a system voltage supplying node and a ground node, in a first state of a charging mode, the first battery and the second battery are connected in serial between a charge input node and the ground node with a first terminal of the second battery being connected to the system voltage supplying node, and in a second state of the charging mode, the first battery and the second battery are connected in serial between the charge input node and the ground node with a first terminal of the first battery being connected to the system voltage supplying node.

    Power supplying system with fast charging capability and low power consumption
    9.
    发明公开
    Power supplying system with fast charging capability and low power consumption 审中-公开

    公开(公告)号：US20230261483A1

    公开(公告)日：2023-08-17

    申请号：US18096018

    申请日：2023-01-12

    Applicant: MEDIATEK INC.

    Inventor： Yan-Liang Ji

    IPC: H02J7/00

    CPC classification number: H02J7/0024 ,  H02J7/00712

    Abstract: A power supplying system for supplying power in an electronic device includes a plurality of rechargeable batteries coupled to a functional block of the electronic device. The rechargeable batteries at least include a first battery and a second batter. In a normal mode, the first battery and the second battery are connected in parallel between a system voltage supplying node and a ground node, and in a charging mode, the first battery and the second battery are connected in serial between a charge input node and the ground node.

    MOS transistor structure with hump-free effect
    10.
    发明授权
    MOS transistor structure with hump-free effect 有权

    公开(公告)号：US11705514B2

    公开(公告)日：2023-07-18

    申请号：US15138683

    申请日：2016-04-26

    Applicant: MediaTek Inc.

    Inventor： Cheng Hua Lin ,  Yan-Liang Ji

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/78

    Abstract: A MOS transistor structure is provided. The MOS transistor structure includes a semiconductor substrate having an active area including a first edge and a second edge opposite thereto. A gate layer is disposed on the active area of the semiconductor substrate and has a first edge extending across the first and second edges of the active area. A source region having a first conductivity type is in the active area at a side of the first edge of the gate layer and between the first and second edges of the active area. First and second heavily doped regions of a second conductivity type are in the active area adjacent to the first and second edges thereof, respectively, and spaced apart from each other by the source region.

Patent Agency Ranking