公开(公告)号：US10396166B2

公开(公告)日：2019-08-27

申请号：US15425207

申请日：2017-02-06

Applicant: MEDIATEK INC.

Inventor： Cheng Hua Lin ,  Yan-Liang Ji

IPC: H01L29/40 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.

公开(公告)号：US09825168B2

公开(公告)日：2017-11-21

申请号：US15070289

申请日：2016-03-15

Applicant: MediaTek Inc.

Inventor： Cheng Hua Lin ,  Yan-Liang Ji

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66681

Abstract: A semiconductor device includes a semiconductor substrate and a first well region formed in the semiconductor substrate. An insulator is formed in and over a portion of the first well region and a second well region is formed in the first well region at a first side of the insulator. A first doped region is formed in the second well region, and a second doped region is formed in the first well region at a second side opposite the first side of the insulator. A gate structure is formed over the insulator, the first well region between the second well region and the insulator, and the second well region. An isolation element is formed in the semiconductor substrate, surrounding the first well region and the second well region. The first and second doped regions are formed with asymmetric configurations from a top view.

公开(公告)号：US11705514B2

公开(公告)日：2023-07-18

申请号：US15138683

申请日：2016-04-26

Applicant: MediaTek Inc.

Inventor： Cheng Hua Lin ,  Yan-Liang Ji

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/78

Abstract: A MOS transistor structure is provided. The MOS transistor structure includes a semiconductor substrate having an active area including a first edge and a second edge opposite thereto. A gate layer is disposed on the active area of the semiconductor substrate and has a first edge extending across the first and second edges of the active area. A source region having a first conductivity type is in the active area at a side of the first edge of the gate layer and between the first and second edges of the active area. First and second heavily doped regions of a second conductivity type are in the active area adjacent to the first and second edges thereof, respectively, and spaced apart from each other by the source region.

公开(公告)号：US10418480B2

公开(公告)日：2019-09-17

申请号：US15426414

申请日：2017-02-07

Applicant: MEDIATEK INC.

Inventor： Chu-Wei Hu ,  Cheng Hua Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A first doped region and a second doped region are formed on the first well doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and adjacent to the first doped region. A second gate structure overlaps the first gate structure and the first well doped region. A third gate structure is formed beside the second gate structure and close to the second doped region. The top surface of the first well doped region between the second gate structure and the third gate structure avoids having any gate structure and silicide formed thereon.