公开(公告)号：US10177225B2

公开(公告)日：2019-01-08

申请号：US15206399

申请日：2016-07-11

Applicant: MEDIATEK Inc.

Inventor： Yan-Liang Ji ,  Cheng-Hua Lin ,  Puo-Yu Chiang

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L23/535 ,  H01L29/36 ,  H01L29/423

Abstract: The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface. first doped region embedded in the semiconductor substrate. The second doped region is embedded in the semiconductor substrate. The gate structure is formed on the upper surface. The dielectric layer is formed above the upper surface and located between the first doped region and the second doped region. The conductive portion is formed on the dielectric layer.

公开(公告)号：US09029223B1

公开(公告)日：2015-05-12

申请号：US14582608

申请日：2014-12-24

Applicant: MediaTek Inc.

Inventor： Puo-Yu Chiang ,  Yan-Liang Ji

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/266 ,  H01L29/06

CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835

Abstract: A method for fabricating a metal-oxide-semiconductor (MOS) device with isolated drain. The method performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate, exposing portions of the semiconductor substrate; performing a first ion implant process on the portions of the semiconductor substrate exposed by the first patterned mask layer; performing a second ion implant process to a second well region exposed, forming a fourth well region between the first well region and the second well region; performing a third implant process to the second well region, forming a fifth well region overlying the fourth well region; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.

Abstract translation: 一种用于制造具有隔离漏极的金属氧化物半导体（MOS）器件的方法。 该方法执行以下操作：形成嵌入在半导体衬底的一部分中的第一阱区; 在所述半导体衬底上形成第一图案化掩模层，暴露所述半导体衬底的部分; 在由第一图案化掩模层曝光的半导体衬底的部分上执行第一离子注入工艺; 对暴露的第二阱区域执行第二离子注入工艺，在第一阱区域和第二阱区域之间形成第四阱区域; 对所述第二阱区域执行第三注入工艺，形成覆盖所述第四阱区域的第五阱区域; 在所述第三阱区域的一部分中形成源极区域; 以及在所述第五阱区的一部分中形成漏极区。

公开(公告)号：US09570630B2

公开(公告)日：2017-02-14

申请号：US13927468

申请日：2013-06-26

Applicant: MediaTek Inc.

Inventor： Puo-Yu Chiang

IPC: H01L29/872 ,  H01L29/739

CPC classification number: H01L29/872 ,  H01L29/7391

Abstract: The invention provides a Schottky diode structure. An exemplary embodiment of a Schottky diode structure includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed on the first well region. A first electrode is disposed on the active region, covering the first doped region. A second electrode is disposed on the active region, contacting to the first well region. A gate structure is disposed on the first well region. A second doped region, having a second conductive type opposite to the first conductive type, and is formed on the first well region. The gate structure and the second doped region are disposed between the first and second electrodes.

Abstract translation: 本发明提供一种肖特基二极管结构。 肖特基二极管结构的示例性实施例包括具有有源区的半导体衬底。 在有源区中形成具有第一导电类型的第一阱区。 具有第一导电类型的第一掺杂区形成在第一阱区上。 第一电极设置在有源区上，覆盖第一掺杂区。 第二电极设置在有源区上，与第一阱区接触。 栅极结构设置在第一阱区上。 第二掺杂区，具有与第一导电类型相反的第二导电类型，并形成在第一阱区上。 栅极结构和第二掺杂区域设置在第一和第二电极之间。

公开(公告)号：US20170047398A1

公开(公告)日：2017-02-16

申请号：US15206399

申请日：2016-07-11

Applicant: MEDIATEK Inc.

Inventor： Yan-Liang Ji ,  Cheng-Hua Lin ,  Puo-Yu Chiang

IPC: H01L29/06 ,  H01L21/768 ,  H01L29/423 ,  H01L29/36 ,  H01L23/535

CPC classification number: H01L29/0653 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/36 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42356 ,  H01L29/7835

Abstract: The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface. first doped region embedded in the semiconductor substrate. The second doped region is embedded in the semiconductor substrate. The gate structure is formed on the upper surface. The dielectric layer is formed above the upper surface and located between the first doped region and the second doped region. The conductive portion is formed on the dielectric layer.

Abstract translation: 电子部件包括半导体基板，第一掺杂区域，第二掺杂区域，栅极结构，电介质层和导电部分。 半导体衬底具有上表面。 第一掺杂区域嵌入在半导体衬底中。 第二掺杂区域嵌入在半导体衬底中。 栅极结构形成在上表面上。 电介质层形成在上表面上方并位于第一掺杂区和第二掺杂区之间。 导电部分形成在电介质层上。

公开(公告)号：US09006068B1

公开(公告)日：2015-04-14

申请号：US14582626

申请日：2014-12-24

Applicant: MediaTek Inc

Inventor： Puo-Yu Chiang ,  Yan-Liang Ji

IPC: H01L21/266 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835

Abstract: A method for fabricating a metal-oxide-semiconductor (MOS) device, performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate; performing a first ion implant process on two portions of the semiconductor substrate exposed by the first patterned mask layer; removing the first patterned mask layer and forming a second patterned mask layer over the semiconductor substrate, exposing a portion of the third well region; performing a second ion implant process to the portion of the third well region exposed by the second patterned mask layer; performing a third implant process to the portion of the third well region exposed by the second patterned mask layer; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.

Abstract translation: 一种制造金属氧化物半导体（MOS）器件的方法，执行以下操作：形成嵌入在半导体衬底的一部分中的第一阱区; 在所述半导体衬底上形成第一图案化掩模层; 在由第一图案化掩模层曝光的半导体衬底的两个部分上执行第一离子注入工艺; 去除所述第一图案化掩模层并在所述半导体衬底上形成第二图案化掩模层，暴露所述第三阱区域的一部分; 对由第二图案化掩模层暴露的第三阱区的部分执行第二离子注入工艺; 对由第二图案化掩模层暴露的第三阱区的部分执行第三注入工艺; 在所述第三阱区域的一部分中形成源极区域; 以及在所述第五阱区的一部分中形成漏极区。

公开(公告)号：US09006825B1

公开(公告)日：2015-04-14

申请号：US14039161

申请日：2013-09-27

Applicant: MediaTek Inc.

Inventor： Puo-Yu Chiang ,  Yan-Liang Ji

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835

Abstract: A MOS device with an isolated drain includes: a semiconductor substrate having a first conductivity type; a first well region embedded in a first portion of the semiconductor substrate, having a second conductivity type; a second well region disposed in a second portion of the semiconductor substrate, overlying the first well region and having the first conductivity type; a third well region disposed in a third portion of the semiconductor substrate, overlying the first well region having the second conductivity type; a fourth well region disposed in a fourth portion of the semiconductor substrate between the first and third well regions, having the first conductivity type; a gate stack formed over the semiconductor substrate; a source region disposed in a portion of the second well region, having the second conductivity type; and a drain region disposed in a portion of the fourth well region, having the second conductivity type.

Abstract translation: 具有隔离漏极的MOS器件包括：具有第一导电类型的半导体衬底; 嵌入在半导体衬底的第一部分中的第一阱区，具有第二导电类型; 第二阱区，设置在所述半导体衬底的第二部分中，覆盖所述第一阱区并且具有所述第一导电类型; 设置在半导体衬底的第三部分中的第三阱区，覆盖具有第二导电类型的第一阱区; 第四阱区，设置在具有第一导电类型的第一和第三阱区之间的半导体衬底的第四部分中; 形成在半导体衬底上的栅叠层; 源区域，其设置在所述第二阱区域的具有所述第二导电类型的部分中; 以及设置在具有第二导电类型的第四阱区域的一部分中的漏极区域。

公开(公告)号：US10008593B2

公开(公告)日：2018-06-26

申请号：US14576301

申请日：2014-12-19

Applicant: MediaTek Inc.

Inventor： Chih-Chung Chiu ,  Puo-Yu Chiang

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7835

Abstract: A semiconductor device includes a well region of a first conductivity type, having a first depth, formed in a substrate. A source contact region of a second conductivity type is formed in the well region. A drift region of the second conductivity type, having a second depth greater than 50% of the first depth, is formed in the substrate adjacent to the well region. A drain contact region of the second conductivity type is formed in the drift region. A gate electrode is formed on the substrate between the source contact region and the drain contact region. The drain contact region is spaced apart from the gate electrode and the source contact region is adjacent to the gate electrode. Furthermore, a method of fabricating a semiconductor device is also provided. The method includes performing a multi-step implantation process to form a drift region.

公开(公告)号：US20160056285A1

公开(公告)日：2016-02-25

申请号：US14467054

申请日：2014-08-25

Applicant: MEDIATEK INC.

Inventor： Puo-Yu Chiang

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7835 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7816

Abstract: A HVMOS transistor structure includes a semiconductor substrate; a gate overlying the semiconductor substrate; a gate dielectric layer between the gate and the semiconductor substrate; a sidewall spacer on each sidewall of the gate; a drain structure in the semiconductor substrate on one side of the gate; an ion well of the first conductivity type in the semiconductor substrate; a source structure in the semiconductor substrate being space apart from the drain structure; and a channel region between the drain structure and the source structure, wherein the channel region substantially consisting of two gate-overlapping regions of the first conductivity type having doping concentrations different from each other.

Abstract translation: HVMOS晶体管结构包括半导体衬底; 覆盖半导体衬底的栅极; 在栅极和半导体衬底之间的栅介质层; 栅极的每个侧壁上的侧壁间隔物; 栅极一侧的半导体衬底中的漏极结构; 半导体衬底中的第一导电类型的离子阱; 所述半导体衬底中的源极结构与所述漏极结构间隔开; 以及在漏极结构和源极结构之间的沟道区域，其中所述沟道区域基本上由具有彼此不同的掺杂浓度的第一导电类型的两个栅极重叠区域组成。