公开(公告)号：US10373949B2

公开(公告)日：2019-08-06

申请号：US15677190

申请日：2017-08-15

Applicant: MEDIATEK Inc.

Inventor： Yan-Liang Ji ,  Cheng-Hua Lin ,  Chih-Chung Chiu

IPC: H01L27/06 ,  H01L29/06 ,  H01L23/528 ,  H01L21/8234 ,  H01L29/66 ,  H01L49/02

Abstract: A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.

公开(公告)号：US20180240794A1

公开(公告)日：2018-08-23

申请号：US15677190

申请日：2017-08-15

Applicant: MEDIATEK Inc.

Inventor： Yan-Liang Ji ,  Cheng-Hua Lin ,  Chih-Chung Chiu

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/0629 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0617 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/665

Abstract: A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.

公开(公告)号：US10008593B2

公开(公告)日：2018-06-26

申请号：US14576301

申请日：2014-12-19

Applicant: MediaTek Inc.

Inventor： Chih-Chung Chiu ,  Puo-Yu Chiang

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7835

Abstract: A semiconductor device includes a well region of a first conductivity type, having a first depth, formed in a substrate. A source contact region of a second conductivity type is formed in the well region. A drift region of the second conductivity type, having a second depth greater than 50% of the first depth, is formed in the substrate adjacent to the well region. A drain contact region of the second conductivity type is formed in the drift region. A gate electrode is formed on the substrate between the source contact region and the drain contact region. The drain contact region is spaced apart from the gate electrode and the source contact region is adjacent to the gate electrode. Furthermore, a method of fabricating a semiconductor device is also provided. The method includes performing a multi-step implantation process to form a drift region.