-
公开(公告)号:US10373949B2
公开(公告)日:2019-08-06
申请号:US15677190
申请日:2017-08-15
Applicant: MEDIATEK Inc.
Inventor: Yan-Liang Ji , Cheng-Hua Lin , Chih-Chung Chiu
IPC: H01L27/06 , H01L29/06 , H01L23/528 , H01L21/8234 , H01L29/66 , H01L49/02
Abstract: A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.
-
公开(公告)号:US10199496B2
公开(公告)日:2019-02-05
申请号:US15411099
申请日:2017-01-20
Applicant: MEDIATEK INC.
Inventor: Cheng-Hua Lin , Yan-Liang Ji , Chih-Wen Hsiung
Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate, a first well region, a second well region, a first gate structure, a first doped region, a second doped region, and a second gate structure. The first well region is formed in a portion of the semiconductor substrate. The second well region is formed in a portion of the first well region. The first gate structure is formed over a portion of the second well region and a portion of the first well region. The first doped region is formed in a portion of the second well region. The second doped region is formed in a portion of the first well region. The second gate structure is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
-
公开(公告)号:US10177225B2
公开(公告)日:2019-01-08
申请号:US15206399
申请日:2016-07-11
Applicant: MEDIATEK Inc.
Inventor: Yan-Liang Ji , Cheng-Hua Lin , Puo-Yu Chiang
IPC: H01L29/06 , H01L29/40 , H01L29/78 , H01L21/768 , H01L23/535 , H01L29/36 , H01L29/423
Abstract: The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface. first doped region embedded in the semiconductor substrate. The second doped region is embedded in the semiconductor substrate. The gate structure is formed on the upper surface. The dielectric layer is formed above the upper surface and located between the first doped region and the second doped region. The conductive portion is formed on the dielectric layer.
-
公开(公告)号:US20180240794A1
公开(公告)日:2018-08-23
申请号:US15677190
申请日:2017-08-15
Applicant: MEDIATEK Inc.
Inventor: Yan-Liang Ji , Cheng-Hua Lin , Chih-Chung Chiu
IPC: H01L27/06 , H01L29/06 , H01L21/8234 , H01L23/528
CPC classification number: H01L27/0629 , H01L21/823475 , H01L21/823481 , H01L23/528 , H01L27/0617 , H01L28/20 , H01L29/0649 , H01L29/665
Abstract: A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.
-
公开(公告)号:US10541328B2
公开(公告)日:2020-01-21
申请号:US16225077
申请日:2018-12-19
Applicant: MEDIATEK INC.
Inventor: Cheng-Hua Lin , Yan-Liang Ji , Chih-Wen Hsiung
IPC: H01L29/00 , H01L29/78 , H01L29/40 , H01L27/06 , H01L49/02 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/66
Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
-
公开(公告)号:US20170047398A1
公开(公告)日:2017-02-16
申请号:US15206399
申请日:2016-07-11
Applicant: MEDIATEK Inc.
Inventor: Yan-Liang Ji , Cheng-Hua Lin , Puo-Yu Chiang
IPC: H01L29/06 , H01L21/768 , H01L29/423 , H01L29/36 , H01L23/535
CPC classification number: H01L29/0653 , H01L21/76895 , H01L23/535 , H01L29/36 , H01L29/402 , H01L29/404 , H01L29/42356 , H01L29/7835
Abstract: The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface. first doped region embedded in the semiconductor substrate. The second doped region is embedded in the semiconductor substrate. The gate structure is formed on the upper surface. The dielectric layer is formed above the upper surface and located between the first doped region and the second doped region. The conductive portion is formed on the dielectric layer.
Abstract translation: 电子部件包括半导体基板,第一掺杂区域,第二掺杂区域,栅极结构,电介质层和导电部分。 半导体衬底具有上表面。 第一掺杂区域嵌入在半导体衬底中。 第二掺杂区域嵌入在半导体衬底中。 栅极结构形成在上表面上。 电介质层形成在上表面上方并位于第一掺杂区和第二掺杂区之间。 导电部分形成在电介质层上。
-
-
-
-
-