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    MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES
    1.
    发明申请
    MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES 失效
    包含两个浮动门结构的晶体管的存储器

    公开(公告)号：US20130069134A1

    公开(公告)日：2013-03-21

    申请号：US13608436

    申请日：2012-09-10

    申请人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    发明人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    IPC分类号： H01L27/11

    CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

    摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

    摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

    Nonvolatile semiconductor memory device and method of manufacturing the same
    2.
    发明授权
    Nonvolatile semiconductor memory device and method of manufacturing the same 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US08546872B2

    公开(公告)日：2013-10-01

    申请号：US13072366

    申请日：2011-03-25

    申请人： Kiwamu Sakuma ,  Atsuhiro Kinoshita

    发明人： Kiwamu Sakuma ,  Atsuhiro Kinoshita

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/7881

    摘要： According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.

    摘要翻译： 根据一个实施例，存储器件包括半导体衬底，第一，第二，第三和第四鳍式堆叠层结构，每个具有堆叠在垂直于半导体衬底的表面的第一方向上的存储串，并且每个延伸到 第二方向平行于半导体衬底的表面，第一部分连接到第一和第二鳍式堆叠层的第二方向上的第一端彼此结合，第二部分连接到第三端的第二端 第四鳍状堆叠层结构，第三部分与第一和第三鳍状堆叠层的第二方向的第二端部连接，第四部分与第二鳍片状堆叠层的第二方向的第二端部连接， 第二和第四鳍式堆叠层结构。

    Nonvolatile semiconductor memory device and method of manufacturing the same
    3.
    发明授权
    Nonvolatile semiconductor memory device and method of manufacturing the same 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US08513725B2

    公开(公告)日：2013-08-20

    申请号：US13236734

    申请日：2011-09-20

    申请人： Kiwamu Sakuma ,  Atsuhiro Kinoshita

    发明人： Kiwamu Sakuma ,  Atsuhiro Kinoshita

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/785 ,  H01L29/792

    摘要： According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

    摘要翻译： 根据一个实施例，存储器件包括第一和第二鳍式堆叠结构，每个第一和第二鳍式堆叠结构每个包括沿第一方向堆叠的第一至第i存储器串（i是除1之外的自然数），第一和第二鳍式堆叠结构 其在第二方向上延伸并且在第三方向上相邻，第一部分连接到第一鳍式堆叠结构的第二方向上的一端，第一部分的第三方向上的宽度大于第一方向上的宽度 第一鳍式堆叠结构的第三方向和与第二鳍式堆叠结构的第二方向的一端连接的第二部分，第二部分的第三方向上的宽度大于第三方向上的宽度 的第二鳍式堆叠结构。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20130015519A1

    公开(公告)日：2013-01-17

    申请号：US13622612

    申请日：2012-09-19

    申请人： Shosuke Fujii ,  Kiwamu Sakuma ,  Jun Fujiki ,  Atsuhiro Kinoshita

    发明人： Shosuke Fujii ,  Kiwamu Sakuma ,  Jun Fujiki ,  Atsuhiro Kinoshita

    IPC分类号： H01L29/792 ,  H01L21/28

    CPC分类号： H01L27/11551 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11578

    摘要： According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.

    摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一至第n半导体层，它们沿垂直于半导体衬底的表面的第一方向堆叠并且沿与半导体衬底的表面平行的第二方向延伸， 电极，其沿第一方向沿着第一至第n半导体层的侧表面延伸，第一至第n半导体层的侧表面在垂直于第一和第二方向的第三方向上暴露，以及第一至第n- 分别位于第一至第n半导体层之间的电荷存储层和电极。 第一至第n电荷存储层在第一至第n半导体层之间的区域中彼此分离。

    Memory including transistors with double floating gate structures
    8.
    发明授权
    Memory including transistors with double floating gate structures 失效
    存储器包括具有双浮栅结构的晶体管

    公开(公告)号：US08610196B2

    公开(公告)日：2013-12-17

    申请号：US13608436

    申请日：2012-09-10

    申请人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    发明人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    IPC分类号： H01L27/11

    CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

    摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

    摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

    Programmable logic switch
    9.
    发明授权
    Programmable logic switch 有权
    可编程逻辑开关

    公开(公告)号：US08432186B1

    公开(公告)日：2013-04-30

    申请号：US13484639

    申请日：2012-05-31

    申请人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Shinichi Yasuda ,  Masato Oda ,  Haruka Kusai ,  Kiwamu Sakuma

    发明人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Shinichi Yasuda ,  Masato Oda ,  Haruka Kusai ,  Kiwamu Sakuma

    IPC分类号： H03K19/173

    CPC分类号： H03K19/018585 ,  G11C5/146 ,  G11C16/10 ,  G11C16/12 ,  H03K19/1737

    摘要： One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.

    摘要翻译： 一个实施例提供一种可编程逻辑开关，其中在同一个阱中形成第一非易失性存储器和第二非易失性存储器，并且其中将第一非易失性存储器从擦除状态改变为写入状态，并使第二非易失性存储器处于 擦除状态时，将第一写入电压施加到与第一和第二非易失性存储器的栅电极连接的第一线，第二写入电压被施加到连接到第一非易失性存储器中的源极的第二线，并且第三写入 低于第二写入电压的电压被施加到连接到第二非易失性存储器的源极的第四线路。

    SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20120075928A1

    公开(公告)日：2012-03-29

    申请号：US13246996

    申请日：2011-09-28

    申请人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

    发明人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

    IPC分类号： H01L29/792 ,  G11C11/34 ,  G11C11/412

    CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/11568 ,  H01L29/4234

    摘要： In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.

    摘要翻译： 在半导体层中，通过向第一电极施加第一电位，向所有背栅电极施加低于第一电位的第二电位，向第一电极施加高于第一电位的第三电位，写入信息 到（i-1）个前栅电极，并且将第二和第三电位之间的第四电位施加到第i个和后续的前栅电极，其中“i”是正整数，并且识别信息的特定位置 要写