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    Semiconductor device and method of manufacturing the same
    2.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08669162B2

    公开(公告)日：2014-03-11

    申请号：US13401478

    申请日：2012-02-21

    申请人： Yukio Nakabayashi ,  Toshinori Numata

    发明人： Yukio Nakabayashi ,  Toshinori Numata

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/785

    摘要： A method of manufacturing a semiconductor device according to an embodiment includes: forming a plurality of semiconductor layers located at a distance from one another on a first insulating film; forming a gate insulating film that covers both side faces and an upper face of each of the semiconductor layers; forming a gate electrode of a polysilicon film to cover the gate insulating film of each of the semiconductor layers; forming a second insulating film on an entire surface; exposing an upper face of the gate electrode by performing selective etching on a portion of the second insulating film; siliciding the gate electrode; and forming a stress applying film that applies a stress in a direction perpendicular to the extending direction of each of the semiconductor layers and parallel to an upper face of the first insulating film.

    摘要翻译： 根据实施例的制造半导体器件的方法包括：在第一绝缘膜上形成彼此间隔一定距离的多个半导体层; 形成覆盖所述半导体层的两个侧面和上表面的栅极绝缘膜; 形成多晶硅膜的栅电极以覆盖每个半导体层的栅极绝缘膜; 在整个表面上形成第二绝缘膜; 通过对所述第二绝缘膜的一部分进行选择性蚀刻来暴露所述栅电极的上表面; 硅化栅电极; 以及形成应力施加膜，所述应力施加膜在垂直于每个所述半导体层的延伸方向的方向上施加应力，并平行于所述第一绝缘膜的上表面。

    FIELD EFFECT TRANSISTOR
    3.
    发明申请
    FIELD EFFECT TRANSISTOR 失效
    场效应晶体管

    公开(公告)号：US20080150040A1

    公开(公告)日：2008-06-26

    申请号：US12034822

    申请日：2008-02-21

    申请人： Yukio Nakabayashi ,  Kazumi Nishinohara ,  Atsuhiro Kinoshita ,  Junji Koga

    发明人： Yukio Nakabayashi ,  Kazumi Nishinohara ,  Atsuhiro Kinoshita ,  Junji Koga

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66643 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/78621

    摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.

    摘要翻译： 场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域 和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极， 并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。

    Field effect transistor
    4.
    发明授权
    Field effect transistor 有权
    场效应晶体管

    公开(公告)号：US07358550B2

    公开(公告)日：2008-04-15

    申请号：US11081348

    申请日：2005-03-16

    申请人： Yukio Nakabayashi ,  Kazumi Nishinohara ,  Atsuhiro Kinoshita ,  Junji Koga

    发明人： Yukio Nakabayashi ,  Kazumi Nishinohara ,  Atsuhiro Kinoshita ,  Junji Koga

    IPC分类号： H01L29/76

    CPC分类号： H01L29/785 ,  H01L29/66643 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/78621

    摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.

    摘要翻译： 场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域 和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极， 并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。

    Semiconductor device manufacturing method
    6.
    发明授权
    Semiconductor device manufacturing method 有权
    半导体器件制造方法

    公开(公告)号：US08492219B2

    公开(公告)日：2013-07-23

    申请号：US13487295

    申请日：2012-06-04

    申请人： Masumi Saitoh ,  Toshinori Numata ,  Yukio Nakabayashi

    发明人： Masumi Saitoh ,  Toshinori Numata ,  Yukio Nakabayashi

    IPC分类号： H01L21/8234 ,  H01L21/337 ,  H01L21/8232 ,  H01L21/336 ,  H01L21/00

    CPC分类号： H01L27/0207 ,  H01L21/266 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66628 ,  H01L29/785

    摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.

    摘要翻译： 在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极 形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案， 执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源 在栅电极的两侧形成有引线区域。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20120228637A1

    公开(公告)日：2012-09-13

    申请号：US13411789

    申请日：2012-03-05

    申请人： YUKIO NAKABAYASHI ,  TAKASHI SHINOHE ,  ATSUKO YAMASHITA

    发明人： YUKIO NAKABAYASHI ,  TAKASHI SHINOHE ,  ATSUKO YAMASHITA

    IPC分类号： H01L29/161 ,  H01L21/336

    CPC分类号： H01L29/66068 ,  H01L21/046 ,  H01L21/0475 ,  H01L29/7827

    摘要： A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.

    摘要翻译： 实施例的半导体器件包括具有第一和第二主表面的第一导电型碳化硅衬底，形成在第一主表面上的第一导电型碳化硅层，形成在碳化硅层中的第二导电型第一碳化硅区， 以及形成在第一碳化硅区域中的第一导电类型的第二碳化硅区域。 该器件包括穿过第一和第二碳化硅区域的沟槽以及形成在沟槽的底部和侧表面上的第二导电类型的第三碳化硅区域。 第三碳化硅区域与第一碳化硅区域接触，并且形成在沟槽和碳化硅层之间。 此外，该器件包括形成在沟槽中的栅极绝缘膜，栅电极，第一电极和第二电极。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20120146114A1

    公开(公告)日：2012-06-14

    申请号：US13401478

    申请日：2012-02-21

    申请人： Yukio NAKABAYASHI ,  Toshinori Numata

    发明人： Yukio NAKABAYASHI ,  Toshinori Numata

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/785

    摘要： A method of manufacturing a semiconductor device according to an embodiment includes: forming a plurality of semiconductor layers located at a distance from one another on a first insulating film; forming a gate insulating film that covers both side faces and an upper face of each of the semiconductor layers; forming a gate electrode of a polysilicon film to cover the gate insulating film of each of the semiconductor layers; forming a second insulating film on an entire surface; exposing an upper face of the gate electrode by performing selective etching on a portion of the second insulating film; siliciding the gate electrode; and forming a stress applying film that applies a stress in a direction perpendicular to the extending direction of each of the semiconductor layers and parallel to an upper face of the first insulating film.

    摘要翻译： 根据实施例的制造半导体器件的方法包括：在第一绝缘膜上形成彼此间隔一定距离的多个半导体层; 形成覆盖所述半导体层的两个侧面和上表面的栅极绝缘膜; 形成多晶硅膜的栅电极以覆盖每个半导体层的栅极绝缘膜; 在整个表面上形成第二绝缘膜; 通过对所述第二绝缘膜的一部分进行选择性蚀刻来暴露所述栅电极的上表面; 硅化栅电极; 以及形成应力施加膜，所述应力施加膜在垂直于每个所述半导体层的延伸方向的方向上施加应力，并平行于所述第一绝缘膜的上表面。

    Multi-gate field effect transistor and method for manufacturing the same
    10.
    发明授权
    Multi-gate field effect transistor and method for manufacturing the same 有权
    多栅极场效应晶体管及其制造方法

    公开(公告)号：US07781274B2

    公开(公告)日：2010-08-24

    申请号：US12210328

    申请日：2008-09-15

    申请人： Yukio Nakabayashi ,  Ken Uchida

    发明人： Yukio Nakabayashi ,  Ken Uchida

    IPC分类号： H01L21/00

    CPC分类号： H01L29/66795 ,  H01L29/785

    摘要： A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.

    摘要翻译： 多栅极场效应晶体管包括：平行布置在衬底上的多个半导体层; 形成在每个半导体层中的源区和漏区; 沟道区域，每个沟道区域设置在每个半导体层中的源极区域和漏极区域之间; 保护膜分别设置在每个通道区域的上表面上; 栅极绝缘膜各自设置在每个沟道区域的两个侧面上; 设置在每个沟道区域的两个侧面上的多个栅电极，以便设置在每个沟道区域的上表面上方的栅极绝缘膜，以便插入保护膜，并且容纳金属元件; 连接所述栅电极的上表面的连接部; 以及连接到连接部分的栅极线。