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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20120146053A1

    公开(公告)日：2012-06-14

    申请号：US13237697

    申请日：2011-09-20

    申请人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi ,  Kensuke Ota

    发明人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi ,  Kensuke Ota

    IPC分类号： H01L29/161 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7843

    摘要： A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls.

    摘要翻译： 根据实施例的半导体器件包括半导体衬底，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，形成在栅电极两侧的第一栅极侧壁和源极/漏极半导体 层，形成在半导体衬底上，以与栅电极夹住第一栅极侧壁。 此外，第二栅极侧壁设置在栅电极两侧的第一栅极侧壁和源极/漏极半导体层上，其中每个第二栅极侧壁与每个第一栅极侧壁的边界在侧表面终止 并且每个第二栅极侧壁具有比每个第一栅极侧壁更小的杨氏模量和更低的介电常数。

    SEMICONDUCTOR DEVICE MANUFACTURING METHOD
    3.
    发明申请
    SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
    半导体器件制造方法

    公开(公告)号：US20120282743A1

    公开(公告)日：2012-11-08

    申请号：US13487295

    申请日：2012-06-04

    申请人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi

    发明人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi

    IPC分类号： H01L21/336

    CPC分类号： H01L27/0207 ,  H01L21/266 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66628 ,  H01L29/785

    摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.

    摘要翻译： 在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极 形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案， 执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源 在栅电极的两侧形成有引线区域。

    Semiconductor device manufacturing method
    4.
    发明授权
    Semiconductor device manufacturing method 有权
    半导体器件制造方法

    公开(公告)号：US08492219B2

    公开(公告)日：2013-07-23

    申请号：US13487295

    申请日：2012-06-04

    申请人： Masumi Saitoh ,  Toshinori Numata ,  Yukio Nakabayashi

    发明人： Masumi Saitoh ,  Toshinori Numata ,  Yukio Nakabayashi

    IPC分类号： H01L21/8234 ,  H01L21/337 ,  H01L21/8232 ,  H01L21/336 ,  H01L21/00

    CPC分类号： H01L27/0207 ,  H01L21/266 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66628 ,  H01L29/785

    摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.

    摘要翻译： 在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极 形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案， 执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源 在栅电极的两侧形成有引线区域。

    Semiconductor device and method of manufacturing the same
    6.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08669162B2

    公开(公告)日：2014-03-11

    申请号：US13401478

    申请日：2012-02-21

    申请人： Yukio Nakabayashi ,  Toshinori Numata

    发明人： Yukio Nakabayashi ,  Toshinori Numata

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/785

    摘要： A method of manufacturing a semiconductor device according to an embodiment includes: forming a plurality of semiconductor layers located at a distance from one another on a first insulating film; forming a gate insulating film that covers both side faces and an upper face of each of the semiconductor layers; forming a gate electrode of a polysilicon film to cover the gate insulating film of each of the semiconductor layers; forming a second insulating film on an entire surface; exposing an upper face of the gate electrode by performing selective etching on a portion of the second insulating film; siliciding the gate electrode; and forming a stress applying film that applies a stress in a direction perpendicular to the extending direction of each of the semiconductor layers and parallel to an upper face of the first insulating film.

    摘要翻译： 根据实施例的制造半导体器件的方法包括：在第一绝缘膜上形成彼此间隔一定距离的多个半导体层; 形成覆盖所述半导体层的两个侧面和上表面的栅极绝缘膜; 形成多晶硅膜的栅电极以覆盖每个半导体层的栅极绝缘膜; 在整个表面上形成第二绝缘膜; 通过对所述第二绝缘膜的一部分进行选择性蚀刻来暴露所述栅电极的上表面; 硅化栅电极; 以及形成应力施加膜，所述应力施加膜在垂直于每个所述半导体层的延伸方向的方向上施加应力，并平行于所述第一绝缘膜的上表面。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US08467241B2

    公开(公告)日：2013-06-18

    申请号：US13246996

    申请日：2011-09-28

    申请人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

    发明人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

    IPC分类号： G11C11/34

    CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/11568 ,  H01L29/4234

    摘要： In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.

    摘要翻译： 在半导体层中，通过向第一电极施加第一电位，向所有背栅电极施加低于第一电位的第二电位，向第一电极施加高于第一电位的第三电位，写入信息 到（i-1）个前栅电极，并且将第二和第三电位之间的第四电位施加到第i个和后续的前栅电极，其中“i”是正整数，并且识别信息的特定位置 要写

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20120075928A1

    公开(公告)日：2012-03-29

    申请号：US13246996

    申请日：2011-09-28

    申请人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

    发明人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

    IPC分类号： H01L29/792 ,  G11C11/34 ,  G11C11/412

    CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/11568 ,  H01L29/4234

    摘要： In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.

    摘要翻译： 在半导体层中，通过向第一电极施加第一电位，向所有背栅电极施加低于第一电位的第二电位，向第一电极施加高于第一电位的第三电位，写入信息 到（i-1）个前栅电极，并且将第二和第三电位之间的第四电位施加到第i个和后续的前栅电极，其中“i”是正整数，并且识别信息的特定位置 要写

    Fin-type channel transistor and method of manufacturing the same
    9.
    发明授权
    Fin-type channel transistor and method of manufacturing the same 失效
    鳍型沟道晶体管及其制造方法

    公开(公告)号：US07521752B2

    公开(公告)日：2009-04-21

    申请号：US11384269

    申请日：2006-03-21

    申请人： Atsuhiro Kinoshita ,  Junji Koga ,  Yukio Nakabayashi

    发明人： Atsuhiro Kinoshita ,  Junji Koga ,  Yukio Nakabayashi

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618

    摘要： It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions. There are provided: a first semiconductor layer of a first conductivity type in a substantially a rectangular solid shape formed on a substrate; a gate electrode formed on a pair of first side portions of the first semiconductor layer facing to each other with a gate insulating film being placed between the gate electrode and the first side portions; a second semiconductor layer of the first conductivity type connected to bottom portions of a pair of second side portions of the first semiconductor layer placed in a substantially perpendicular direction with respect to the first side portions, the second semiconductor layer extending along the substantially perpendicular direction; a first impurity region of a second conductivity type formed in the second semiconductor layer; second impurity regions formed on the pair of side portions of the first semiconductor layer and connected to the first impurity region; and a channel region formed between the second impurity regions of the first semiconductor layer.

    摘要翻译： 可以将杂质可靠地注入到杂质形成区域中，并且在源极和漏极区域的整个部分上形成自对准的硅化物。 提供：形成在基板上的基本为矩形的实心形状的第一导电类型的第一半导体层; 形成在所述第一半导体层的一对第一侧部分上的栅电极，栅极绝缘膜位于所述栅电极和所述第一侧部之间，所述栅极绝缘膜彼此面对; 所述第一导电类型的第二半导体层连接到所述第一半导体层的一对第二侧部的与所述第一侧部大致垂直的方向上的第二侧部的底部，所述第二半导体层沿着大致垂直的方向延伸; 形成在第二半导体层中的第二导电类型的第一杂质区; 第二杂质区，形成在第一半导体层的一对侧部并连接到第一杂质区; 以及形成在第一半导体层的第二杂质区之间的沟道区。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20080227241A1

    公开(公告)日：2008-09-18

    申请号：US12043327

    申请日：2008-03-06

    申请人： Yukio Nakabayashi ,  Junji Koga ,  Atsuhiro Kinoshita

    发明人： Yukio Nakabayashi ,  Junji Koga ,  Atsuhiro Kinoshita

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/66795

    摘要： A semiconductor device fabrication method for forming on a wafer-bonded substrate p- and n-type FinFETs each having a channel plane exhibiting high carrier mobility is disclosed. First, prepare two semiconductor wafers. Each wafer has a surface of {100} crystalline orientation and a direction. These wafers are surface-bonded together so that the directions of upper and lower wafers cross each other at a rotation angle, thereby providing a “hybrid” crystal-oriented substrate. On this substrate, form semiconductor regions, one of which is identical in direction to the upper wafer, and the other of which is equal in direction to the lower wafer. In the one region, form a pFinFET having {100} channel plane. In the other region, form an nFinFET having its channel direction in parallel or perpendicular to that of the pFinFET. A CMOS FinFET structure is thus obtained.

    摘要翻译： 公开了一种半导体器件制造方法，用于在晶片结合的衬底上形成各自具有表现出高载流子迁移率的沟道平面的p型和n型FinFET。 首先，准备两个半导体晶圆。 每个晶片具有{100}晶体取向和<110>方向的表面。 这些晶片被表面粘合在一起，使得上下晶片的<110>方向以旋转角彼此交叉，从而提供“混合”的晶体取向基板。 在该衬底上，形成半导体区域，其中一个在<110>方向上与上晶片相同，另一个在<110>方向与下晶片相等。 在一个区域中，形成具有{100}通道平面的pFinFET。 在另一区域，形成其通道方向平行或垂直于pFinFET的nFinFET。 由此获得CMOS FinFET结构。