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公开(公告)号：US12219889B2
公开(公告)日：2025-02-04
申请号：US17679948
申请日：2022-02-24
Applicant: KIOXIA CORPORATION
Inventor： Masahiro Takahashi , Yoshiaki Asao , Yukihiro Nomura , Daisaburo Takashima
Abstract: A semiconductor storage device includes a memory cell including a core portion that extends in a first direction above a semiconductor substrate; a variable resistance layer that extends in the first direction and is in contact with the core portion; a semiconductor layer that extends in the first direction and is in contact with the variable resistance layer; a first insulator layer that extends in the first direction and is in contact with the semiconductor layer; and a first voltage applying electrode that extends in a second direction orthogonal to the first direction and is in contact with the first insulator layer. The core portion is a vacuum region, or a region containing inert gas.
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公开(公告)号：US11972798B2
公开(公告)日：2024-04-30
申请号：US17681680
申请日：2022-02-25
Applicant: KIOXIA CORPORATION
Inventor： Tomoki Chiba , Daisaburo Takashima , Hidehiro Shiga
CPC classification number: G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0069
Abstract: A nonvolatile memory includes a first memory cell and a second memory cell above the first memory cell. The first memory cell includes a variable resistance layer extending in a first direction, a semiconductor layer extending in the first direction and in contact with the variable resistance layer, an insulator layer extending in the first direction and in contact with the semiconductor layer, and a first voltage applying electrode extending in a second direction and in contact with the insulator layer. The second memory cell includes a second voltage applying electrode in contact with the insulator layer. When a write operation is performed on the first memory cell, a first voltage is applied to the second voltage applying electrode, and when a write operation is performed on the second memory cell, a second voltage, lower than the first voltage, is applied to the first voltage applying electrode.
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公开(公告)号：US11765916B2
公开(公告)日：2023-09-19
申请号：US17348839
申请日：2021-06-16
Applicant: Kioxia Corporation
Inventor： Takahiko Iizuka , Daisaburo Takashima , Ryu Ogiwara , Rieko Funatsuki , Yoshiki Kamata , Misako Morota , Yoshiaki Asao , Yukihiro Nomura
CPC classification number: H10B63/845 , G11C13/003 , G11C13/0004 , G11C13/004 , G11C13/0069 , H10B63/34 , H10N70/066 , H10N70/231 , H10N70/8828 , G11C2213/75
Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
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公开(公告)号：US11742019B2
公开(公告)日：2023-08-29
申请号：US17471981
申请日：2021-09-10
Applicant: Kioxia Corporation
Inventor： Daisaburo Takashima
CPC classification number: G11C13/0009 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/0069
Abstract: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a cell array. The cell array includes an array of a plurality of string blocks. Among the plurality of local string blocks, one local string block includes a block selection transistor and remaining local string blocks do not include a block selection transistor. A gate terminal of the block selection transistor of the one local string block is connected to a block selection line. Signals of two word lines connected to two adjacent string blocks in the bit line direction are common signals. Signals of two block selection lines connected to the two adjacent string blocks are independent of each other.
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公开(公告)号：US11201171B2
公开(公告)日：2021-12-14
申请号：US17008236
申请日：2020-08-31
Applicant: KIOXIA CORPORATION
Inventor： Sumiko Domae , Daisaburo Takashima
IPC: G11C7/06 , H01L27/11597 , H01L27/11592 , H01L27/11509 , H01L29/78 , H01L29/66 , G11C7/18 , H01L27/11514
Abstract: A semiconductor storage device includes a stacked body and a columnar body. The stacked body includes a plurality of conductive layers spaced apart from each other in a stacking direction. The columnar body penetrates the stacked body in the stacking direction. The columnar body includes a columnar ferroelectric film, a semiconductor film disposed between the ferroelectric film and the conductive layers, and an insulating film disposed between the semiconductor film and the conductive layers.
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Patent Agency Ranking
公开(公告)号：US11120866B1
公开(公告)日：2021-09-14
申请号：US17015408
申请日：2020-09-09
Applicant: Kioxia Corporation
Inventor： Takahiko Iizuka , Daisaburo Takashima , Ryu Ogiwara
IPC: G11C11/40 , G11C11/4096 , G11C11/4094 , G11C5/06 , G11C11/408 , G11C5/02 , G11C11/4074
Abstract: According to one embodiment, a driver that sequentially supplies a first voltage, a second voltage higher than the first voltage, and the first voltage to the bit line, during the writing operation to the first memory cell. The driver supplies a third voltage to the second word line and a fourth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if a data is a first data. The driver supplies a fifth voltage to the second word line and a sixth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if the data is a second data. At least the sixth voltage is larger than the fourth voltage or the fifth voltage is larger than the third voltage.
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公开(公告)号：US12213324B2
公开(公告)日：2025-01-28
申请号：US17690387
申请日：2022-03-09
Applicant: Kioxia Corporation
Inventor： Daisaburo Takashima
Abstract: In a nonvolatile semiconductor memory device, in a cell block, a local bit line is connected to a bit line via a select transistor. The local bit line extends in a third direction. A local source line is connected to a source line and extends in the third direction. A plurality of memory cells are connected in parallel between the local source line and the local bit line. Each of the memory cells includes a cell transistor and a resistance change element. The cell transistor has a gate connected to a corresponding one of the word lines and one end connected to one of the local bit line or the local source line. The resistance change element is connected between the other end of the cell transistor and the other one of the local bit line or the local source line.
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公开(公告)号：US12144189B2
公开(公告)日：2024-11-12
申请号：US17939859
申请日：2022-09-07
Applicant: Kioxia Corporation
Inventor： Hidehiro Shiga , Daisaburo Takashima
Abstract: According to a certain embodiment, the 3D stacked semiconductor memory includes: a first electrode line extending in a first direction orthogonal to the semiconductor substrate; a second electrode line adjacent to the first electrode line in a second direction orthogonal to the first direction, and extending in the first direction; a first variable resistance film extending in the first direction and in contact with the second electrode line; a first semiconductor film in contact with the first variable resistance film and the first electrode line; a first potential applying electrode extending in the second direction and in contact with a first insulator layer; a second semiconductor film in contact with a second variable resistance film and the first electrode line; and a second potential applying electrode extending in the second direction and in contact with a second insulator layer. The first and second potential applying electrodes are electrically different nodes.
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公开(公告)号：US12069872B2
公开(公告)日：2024-08-20
申请号：US18231304
申请日：2023-08-08
Applicant: Kioxia Corporation
Inventor： Takahiko Iizuka , Daisaburo Takashima , Ryu Ogiwara , Rieko Funatsuki , Yoshiki Kamata , Misako Morota , Yoshiaki Asao , Yukihiro Nomura
CPC classification number: H10B63/845 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , H10B63/34 , H10N70/066 , H10N70/231 , H10N70/8828 , G11C2213/75
Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
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公开(公告)号：US11948636B2
公开(公告)日：2024-04-02
申请号：US17693935
申请日：2022-03-14
Applicant: Kioxia Corporation
Inventor： Yoshiki Kamata , Yoshiaki Asao , Yukihiro Nomura , Misako Morota , Daisaburo Takashima , Takahiko Iizuka , Shigeru Kawanaka
CPC classification number: G11C13/0069 , G11C5/06 , H10B63/30 , H10N70/826 , G11C2013/0078 , G11C2213/75
Abstract: According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.
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