公开(公告)号：US09583497B2

公开(公告)日：2017-02-28

申请号：US15000563

申请日：2016-01-19

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L29/66 ,  H01L21/74 ,  H01L21/762 ,  H01L27/12 ,  H01L27/06

CPC分类号： H01L27/10829 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/60 ,  H01L28/92 ,  H01L29/0649 ,  H01L29/66181

摘要： A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

摘要翻译： 提供了高k电介质金属沟槽电容器和改进的隔离及其制造方法。 该方法包括在衬底中形成至少一个深沟槽，并用牺牲填充材料和聚合材料填充深沟槽。 该方法还包括继续CMOS工艺，包括形成至少一个晶体管和后端（BEOL）层。 该方法还包括从深沟槽去除牺牲填充材料以暴露侧壁，以及在深沟槽的暴露的侧壁上形成电容器板。 该方法还包括用高k电介质材料衬套电容器板，并用金属材料在高k电介质材料上填充深沟槽的剩余部分。 该方法还包括在填充有金属材料和高k电介质材料的深沟槽上提供钝化层。

公开(公告)号：US20160126305A1

公开(公告)日：2016-05-05

申请号：US14851345

申请日：2015-09-11

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L49/02

CPC分类号： H01L28/40 ,  H01L21/32134 ,  H01L28/86 ,  H01L28/90 ,  H01L28/91

摘要： A semiconductor capacitor and method of fabrication is disclosed. A MIM stack, having alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

摘要翻译： 公开了一种半导体电容器及其制造方法。 在深空腔中形成具有交替的第一和第二类金属层（各自被电介质隔离）的MIM堆叠。 整个堆叠可以被平坦化，然后被图案化以暴露第一区域，并且被选择性地蚀刻以在第一区域内凹陷所有第一金属层。 执行第二选择性蚀刻以在第二区域内凹进所有第二金属层。 蚀刻的凹槽可以用电介质回填。 可以形成单独的电极; 第一电极，形成在所述第一区域中，并且与所有所述第二类型金属层和所述第一类型金属层接触，并且形成在所述第二区域中并与所有第一类金属层接触的第二电极， 所述第二类金属层。

公开(公告)号：US20150221715A1

公开(公告)日：2015-08-06

申请号：US14684533

申请日：2015-04-13

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L49/02 ,  H01L27/108 ,  H01L27/12

CPC分类号： H01L28/60 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181

摘要： A deep trench capacitor structure including an SOI substrate comprising an SOI layer, a rare earth oxide layer, and a bulk substrate, the rare earth oxide layer is located below the SOI layer and above the bulk substrate, and the rare earth oxide layer insulates the SOI layer from the bulk substrate, and a deep trench capacitor extending from a top surface of the SOI layer, through the rare earth oxide layer, down to a location within the bulk substrate, the rare earth oxide layer contacts the deep trench capacitor at an interface between the rare earth oxide layer and the bulk substrate forming an incline away from the deep trench capacitor.

摘要翻译： 包括SOI层，稀土氧化物层和体基板的SOI衬底的深沟槽电容器结构，所述稀土氧化物层位于所述SOI层的下方并且位于所述本体衬底的上方，并且所述稀土氧化物层绝缘 SOI层，以及从SOI层的顶表面延伸穿过稀土氧化物层的深沟槽电容器，到达本体衬底内的位置，稀土氧化物层在 稀土氧化物层与本体衬底之间的界面形成远离深沟槽电容器的斜面。

公开(公告)号：US20140154849A1

公开(公告)日：2014-06-05

申请号：US14175587

申请日：2014-02-07

申请人： International Business Machines Corporation

发明人： Geng Wang ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC分类号： H01L49/02

CPC分类号： H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

摘要： A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

摘要翻译： 提供一种半导体结构，其包括在基底半导体层上包含外延生长的半导体层的材料堆叠，外延生长的半导体层上的电介质层和存在于电介质层上的上半导体层。 存在从上半导体层通过电介质层延伸到与外延生长的半导体层接触的电容器。 电容器包括存在于沟槽的侧壁上的节点电介质和填充沟槽的至少一部分的上电极。 在从上半导体层通过电介质层和外延半导体层延伸到基底半导体层的掺杂区域的接触沟槽中存在衬底接触。 还提供了通过沟槽的侧壁接触基底半导体层的衬底接触。 还提供了形成上述结构的方法。

公开(公告)号：US20130214382A1

公开(公告)日：2013-08-22

申请号：US13845560

申请日：2013-03-18

申请人： International Business Machines Corporation

发明人： Geng Wang ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC分类号： H01L29/06

CPC分类号： H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

摘要： A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

摘要翻译： 提供一种半导体结构，其包括在基底半导体层上包含外延生长的半导体层的材料堆叠，外延生长的半导体层上的电介质层和存在于电介质层上的上半导体层。 存在从上半导体层通过电介质层延伸到与外延生长的半导体层接触的电容器。 电容器包括存在于沟槽的侧壁上的节点电介质和填充沟槽的至少一部分的上电极。 在从上半导体层通过电介质层和外延半导体层延伸到基底半导体层的掺杂区域的接触沟槽中存在衬底接触。 还提供了通过沟槽的侧壁接触基底半导体层的衬底接触。 还提供了形成上述结构的方法。

公开(公告)号：US09397152B2

公开(公告)日：2016-07-19

申请号：US14851345

申请日：2015-09-11

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/8242 ,  H01L49/02

CPC分类号： H01L28/40 ,  H01L21/32134 ,  H01L28/86 ,  H01L28/90 ,  H01L28/91

摘要： A semiconductor capacitor and method of fabrication is disclosed. A MIM stack, having alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

摘要翻译： 公开了一种半导体电容器及其制造方法。 在深空腔中形成具有交替的第一和第二类金属层（各自被电介质隔离）的MIM堆叠。 整个堆叠可以被平坦化，然后被图案化以暴露第一区域，并且被选择性地蚀刻以在第一区域内凹陷所有第一金属层。 执行第二选择性蚀刻以在第二区域内凹陷所有第二金属层。 蚀刻的凹槽可以用电介质回填。 可以形成单独的电极; 第一电极，形成在所述第一区域中，并且与所有所述第二类型金属层和所述第一类型金属层接触，并且形成在所述第二区域中并与所有第一类金属层接触的第二电极， 所述第二类金属层。

公开(公告)号：US20150287721A1

公开(公告)日：2015-10-08

申请号：US14746017

申请日：2015-06-22

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/088 ,  H01L29/06

CPC分类号： H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

摘要： A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

摘要翻译： 介电心轴结构形成在单晶半导体层上。 非晶半导体材料层沉积在单晶半导体层的物理暴露表面和心轴结构的表面上。 可选地，非晶半导体材料层可以注入至少一种不同的半导体材料。 在采用单晶半导体层作为种子层的非晶半导体材料层上进行固相外延，从而形成厚度均匀的外延半导体材料层。 外延半导体材料层的剩余部分是单晶半导体鳍片，并且这些鳍片的厚度是亚光刻的。 在去除介电心轴结构之后，可以采用单晶半导体鳍形成半导体器件。

公开(公告)号：US20140120688A1

公开(公告)日：2014-05-01

申请号：US14146198

申请日：2014-01-02

申请人： International Business Machines Corporation

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L27/1203 ,  H01L29/945

摘要： Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.

摘要翻译： 在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。 在沟槽中形成不透氧层和填充材料层。 从第一沟槽内去除填充材料层和不透氧层。 执行热氧化以将第一沟槽的侧壁下方的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。 在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。 上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。

公开(公告)号：US10079280B2

公开(公告)日：2018-09-18

申请号：US15685450

申请日：2017-08-24

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/167 ,  H01L29/165 ,  H01L21/02 ,  H01L23/535 ,  H01L23/528 ,  H01L29/739 ,  H01L23/485

CPC分类号： H01L29/0847 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31053 ,  H01L23/485 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/083 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/66356 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.

公开(公告)号：US09530701B2

公开(公告)日：2016-12-27

申请号：US14575602

申请日：2014-12-18

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L21/84 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/845 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

摘要： An approach to forming fins for a semiconductor device on a silicon-on-insulator wafer. The approach includes depositing a layer of mandrel material and etching the layer of mandrel material to form a mandrel. The approach includes depositing a layer of a dielectric material on the semiconductor layer and around the mandrel and etching the layer of the dielectric material to form one or more spacers next to the sidewalls of the mandrel, followed by removing the mandrel. Additionally, the approach includes depositing a layer of amorphous semiconductor material around said one or more spacers and heating it to transform into a layer of re-crystallized semiconductor material through solid phase epitaxy. Furthermore, the approach includes removing portions of the layer of re-crystallized semiconductor material from each of the horizontal surfaces of the silicon-on-insulator wafer including the area where the one or more spacers were removed to form one or more fins.

摘要翻译： 在绝缘体上硅晶片上形成用于半导体器件的鳍片的方法。 该方法包括沉积心轴材料层并蚀刻心轴材料层以形成心轴。 该方法包括在半导体层上并围绕心轴沉积介电材料层，并蚀刻电介质材料层以在心轴的侧壁上形成一个或多个间隔物，然后移除心轴。 此外，该方法包括在所述一个或多个间隔物周围沉积非晶半导体材料层并加热，以通过固相外延转变成再结晶的半导体材料层。 此外，该方法包括从绝缘体上硅晶片的每个水平表面去除重结晶半导体材料层的部分，其中包括去除一个或多个间隔物以形成一个或多个鳍片的区域。