公开(公告)号：US10217766B2

公开(公告)日：2019-02-26

申请号：US15794257

申请日：2017-10-26

申请人： International Business Machines Corporation

发明人： Jin Cai ,  Jean-Olivier Plouchart

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L21/027 ,  H01L21/70 ,  H01L21/762 ,  H01L21/84 ,  H01L21/306 ,  H01L21/02 ,  H01L27/13

摘要： A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is constructed using fully depleted silicon on insulator technology having a thin buried oxide layer. Localized areas of the silicon wafer are constructed for radio frequency circuits and/or passive devices. The silicon wafer has a silicon substrate having a resistivity greater than 1 KΩ·cm. The localized areas of the silicon wafer may include a trap rich layer implanted underneath a thin buried oxide layer. The localized areas of the silicon wafer may include a buried oxide layer that is thicker than the thin buried oxide layer. The thicker oxide layer is between 20 and 2000 nm thick. The localized areas of the silicon wafer may include a trap rich layer implanted underneath the thicker buried oxide layer.

公开(公告)号：US09742147B2

公开(公告)日：2017-08-22

申请号：US15205430

申请日：2016-07-08

申请人： International Business Machines Corporation

发明人： Jin Cai ,  Effendi Leobandung ,  Ning Li ,  Tak H. Ning ,  Jean-Olivier Plouchart ,  Devendra K. Sadana

IPC分类号： H01S5/026 ,  G02B6/122 ,  H01S5/30 ,  H01L29/66 ,  H01L29/735 ,  H01L29/786 ,  H01S5/02 ,  G02B6/12

CPC分类号： H01S5/026 ,  G02B6/12004 ,  G02B6/122 ,  G02B2006/12038 ,  H01L21/8258 ,  H01L27/0623 ,  H01L27/082 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1262 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/7317 ,  H01L29/735 ,  H01L29/78654 ,  H01S5/021 ,  H01S5/0261 ,  H01S5/3013

摘要： After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.

公开(公告)号：US09437718B1

公开(公告)日：2016-09-06

申请号：US14709579

申请日：2015-05-12

申请人： International Business Machines Corporation

发明人： Jin Cai ,  Kevin K. Chan ,  Tak H. Ning ,  Jeng-Bang Yau ,  Joonah Yoon

IPC分类号： H01L29/16 ,  H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02 ,  H01L29/735

CPC分类号： H01L29/737 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02645 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

摘要： A method of forming a semiconductor structure includes forming a first seed layer, a second seed layer and an intrinsic base spaced apart from each other and with the intrinsic base located between the first seed layer and the second seed layer on an insulator layer. The method further includes forming an emitter on the first seed layer and on a first vertical surface of the intrinsic base by epitaxially growing the emitter from the first seed layer and the first vertical surface of the intrinsic base, and forming a collector on the second seed layer and on a second vertical surface of the intrinsic base by epitaxially growing the collector from the second seed layer and the second vertical surface of the intrinsic base.

公开(公告)号：US09318585B1

公开(公告)日：2016-04-19

申请号：US14749043

申请日：2015-06-24

申请人： International Business Machines Corporation

发明人： Jin Cai ,  Kevin K. Chan ,  Tak H. Ning ,  Jeng-Bang Yau ,  Joonah Yoon

IPC分类号： H01L29/737 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/737 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02645 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

摘要： A method of forming a semiconductor structure includes forming a first seed layer, a second seed layer and an intrinsic base spaced apart from each other and with the intrinsic base located between the first seed layer and the second seed layer on an insulator layer. The method further includes forming an emitter on the first seed layer and on a first vertical surface of the intrinsic base by epitaxially growing the emitter from the first seed layer and the first vertical surface of the intrinsic base, and forming a collector on the second seed layer and on a second vertical surface of the intrinsic base by epitaxially growing the collector from the second seed layer and the second vertical surface of the intrinsic base.

摘要翻译： 一种形成半导体结构的方法包括：形成第一晶种层，第二晶种层和本征基极彼此间隔开，并且本征基极位于绝缘体层上的第一晶种层和第二籽晶层之间。 该方法还包括通过从第一种子层和本征基底的第一垂直表面外延生长发射体，并在第二种子上形成收集器，在第一籽晶层和本征碱基的第一垂直表面上形成发射体 并且通过从第二种子层和本征基底的第二垂直表面外延生长收集器而在本征基底的第二垂直表面上。

公开(公告)号：US20150295119A1

公开(公告)日：2015-10-15

申请号：US14687489

申请日：2015-04-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

IPC分类号： H01L31/118 ,  G01N27/403 ,  H01L31/0224 ,  H01L31/11 ,  H01L31/0352

CPC分类号： G01T1/247 ,  G01N27/403 ,  G01T3/08 ,  H01L27/14 ,  H01L27/14681 ,  H01L31/022408 ,  H01L31/035272 ,  H01L31/1105 ,  H01L31/115 ,  H01L31/118

摘要： A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

摘要翻译： 传感器包括集电极，发射极和形成为反相双极结型晶体管的基极区势垒，其具有形成基极的基极以激活反相双极结型晶体管。 由集电极，发射极和基极区域与基底基板相对的方式形成电平表面，使得当电平表面暴露于电荷时，在双极结晶体管的操作期间测量电荷。

公开(公告)号：US08912030B2

公开(公告)日：2014-12-16

申请号：US13647547

申请日：2012-10-09

申请人： International Business Machines Corporation

发明人： Jin Cai ,  Effendi Leobandung ,  Tak H. Ning ,  Jeng-Bang Yau

IPC分类号： H01L21/00 ,  H01L27/14 ,  H01L31/0312 ,  H01L27/146 ,  H01L21/02 ,  H01L31/0304 ,  H01L31/028

CPC分类号： H01L27/14 ,  G01T1/026 ,  H01L21/02 ,  H01L27/14689 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/0312 ,  H01L31/1105 ,  H01L31/115

摘要： A radiation dosimeter includes a semiconductor substrate and a buried insulator layer disposed on the semiconductor substrate. The buried insulator layer has a plurality of charge traps. A semiconductor layer is disposed on the buried insulator layer. The semiconductor layer has an emitter, an intrinsic base, and a collector laterally arranged with respect to one another. In response to radiation exposure by the radiation dosimeter, positive charges are trapped in the plurality of charge traps in the buried insulator layer, the amount of positive charge trapped being used to determine the amount of radiation exposure. A method for radiation dosimetry includes providing a radiation dosimeter, where the radiation dosimeter includes a lateral silicon-on-insulator bipolar junction transistor having a buried insulator layer; exposing the radiation dosimeter to ionizing radiation; determining a change in one of the collector current and current gain of the radiation dosimeter; and determining an amount of the radiation dose based on the change in one of the collector current and current gain.

摘要翻译： 辐射剂量计包括设置在半导体衬底上的半导体衬底和掩埋绝缘体层。 掩埋绝缘体层具有多个充电陷阱。 半导体层设置在埋层绝缘体层上。 半导体层具有相对于彼此横向布置的发射极，本征基极和集电极。 响应于辐射剂量计的辐射照射，正电荷被捕获在掩埋绝缘体层中的多个电荷陷阱中，所捕获的正电荷量用于确定辐射暴露量。 辐射剂量测定方法包括提供辐射剂量计，其中辐射剂量计包括具有埋层绝缘体层的横向绝缘体上硅绝缘体双极结型晶体管; 将辐射剂量计暴露于电离辐射; 确定辐射剂量计的集电极电流和电流增益之一的变化; 以及基于集电极电流和电流增益之一的变化来确定辐射剂量的量。

公开(公告)号：US20140362638A1

公开(公告)日：2014-12-11

申请号：US14467165

申请日：2014-08-25

申请人： International Business Machines Corporation

发明人： Jin Cai ,  Kangguo Cheng ,  Robert H. Dennard ,  Ali Khakifirooz ,  Tak H. Ning

IPC分类号： H01L29/786 ,  H01L27/11 ,  G11C11/419

CPC分类号： G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2029/5006 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/0603 ,  H01L29/66833 ,  H01L29/786 ,  H01L29/792

摘要： A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.

摘要翻译： 一种半导体器件，包括存在于其上形成半导体器件的衬底的埋置介质层中的电荷存储元件。 可以使用电荷注入来将电荷引入存在于衬底内的掩埋介电层的电荷存储元件。 注入电荷存储元件的电荷可用于调整存在于基板上的半导体器件阵列内的每个半导体器件的阈值电压（Vt）。

公开(公告)号：US08847348B2

公开(公告)日：2014-09-30

申请号：US13949219

申请日：2013-07-23

申请人： International Business Machines Corporation

发明人： Jin Cai ,  Robert H. Dennard ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L21/70 ,  H01L27/12 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/082

CPC分类号： H01L27/1203 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/082

摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.

摘要翻译： 示例性实施例是互补晶体管反相器电路。 电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。 横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。 横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

公开(公告)号：US08815684B2

公开(公告)日：2014-08-26

申请号：US13708531

申请日：2012-12-07

申请人： International Business Machines Corporation

发明人： Jin Cai ,  Kevin K. Chan ,  Robert H. Dennard ,  Bruce B. Doris ,  Barry P. Linder ,  Ramachandran Muralidhar ,  Ghavam G. Shahidi

IPC分类号： H01L21/205 ,  H01L21/285

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor.

摘要翻译： 一种用于在体衬底中形成翅片晶体管的方法包括在大容量衬底上形成超陡逆行阱（SSRW）。 该阱包括在未掺杂层下形成的第一导电型掺杂剂的掺杂部分。 翅片材料生长在未掺杂的层上。 鳍状结构由翅片材料形成，翅片材料是未掺杂的或掺杂的。 源极和漏极区域邻近翅片结构设置以形成鳍状场效应晶体管。

公开(公告)号：US08809872B2

公开(公告)日：2014-08-19

申请号：US13968570

申请日：2013-08-16

申请人： International Business Machines Corporation

发明人： Jin Cai ,  Kevin K. Chan ,  Robert H. Dannard ,  Bruce B. Doris ,  Barry P. Linder ,  Ramachandran Muralidhar

IPC分类号： H01L29/161 ,  H01L29/36 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor.