公开(公告)号：US09394619B2

公开(公告)日：2016-07-19

申请号：US13795042

申请日：2013-03-12

申请人： Intel Corporation

发明人： Rajen S. Sidhu ,  Mukul P. Renavikar ,  Sandeep B. Sane

IPC分类号： H05K1/09 ,  H05K1/03 ,  C25D3/58 ,  C25D5/02 ,  H05K3/42 ,  H05K3/46 ,  C23C18/48

CPC分类号： C25D3/58 ,  C23C18/48 ,  C25D5/02 ,  H05K3/421 ,  H05K3/4644

摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.

摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括在封装衬底的电介质材料中形成开口，然后使用电镀工艺在开口中镀覆导电互连结构。 电镀工艺可以包括导电金属和掺杂剂，其包含约0.05至10重量％的重量，其中掺杂剂包括镁，锆和锌中的至少一种。

公开(公告)号：US10651108B2

公开(公告)日：2020-05-12

申请号：US15197440

申请日：2016-06-29

申请人： Intel Corporation

发明人： Zhizhong Tang ,  Syadwad Jain ,  Wei Hu ,  Michael A. Schroeder ,  Rajen S. Sidhu ,  Carl L. Deppisch ,  Patrick Nardi ,  Kelly P. Lofgreen ,  Manish Dubey

IPC分类号： H05K5/00 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01L23/42 ,  F28F13/00 ,  F28F21/04 ,  F28F21/02 ,  F28F21/08 ,  F28D21/00

摘要： Devices and methods disclosed herein can include a conductive foam having pores disposed within the conductive foam. The conductive foam can be compressible between an uncompressed thickness and a compressed thickness. The compressed thickness can be ninety-five percent or less of the uncompressed thickness. In one example, a filler can be disposed in the pores of the conductive foam. The filler can include a first thermal conductivity. The first thermal conductivity can be greater than a thermal conductivity of air.

公开(公告)号：US20170207152A1

公开(公告)日：2017-07-20

申请号：US15478064

申请日：2017-04-03

申请人： Intel Corporation

发明人： Thomas J. De Bonis ,  Lilia May ,  Rajen S. Sidhu ,  Mukul P. Renavikar ,  Ashay A. Dani ,  Edward R. Prack ,  Carl L. Deppisch ,  Anna M. Prakash ,  James C. Matayabas ,  Jason Jieping Zhang ,  Srinivasa R. Aravamudhan ,  Chang Lin

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/76802 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/37001 ,  H01L2924/00

摘要： An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

公开(公告)号：US09283641B2

公开(公告)日：2016-03-15

申请号：US13626869

申请日：2012-09-25

申请人： INTEL CORPORATION

发明人： Rajen S. Sidhu ,  Martha A. Dudek ,  Wei Tan

IPC分类号： B23K35/36 ,  B23K35/02 ,  H01L21/48 ,  B23K35/362 ,  H01L23/498

CPC分类号： B23K35/362 ,  B23K35/0244 ,  B23K35/3612 ,  H01L21/4853 ,  H01L23/49816 ,  H01L2224/16225

摘要： Embodiments of the present disclosure are directed towards flux materials for heated solder placement and associated techniques and configurations. In one embodiment, a method includes depositing a flux material on one or more pads of a package substrate, the flux material including a rosin material and a thixotropic agent and depositing one or more solder balls on the flux material disposed on the one or more pads, wherein depositing the one or more solder balls on the flux material is performed at a temperature greater than 80° C., and wherein the rosin material and the thixotropic agent are configured to resist softening at the temperature greater than 80° C. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及用于加热的焊料放置和相关联的技术和构造的助焊剂材料。 在一个实施例中，一种方法包括在封装基板的一个或多个焊盘上沉积焊剂材料，焊剂材料包括松香材料和触变剂，并且将一个或多个焊球沉积在设置在一个或多个焊盘上的焊剂材料上 其中将所述一个或多个焊球沉积在所述焊剂材料上在大于80℃的温度下进行，并且其中所述松香材料和所述触变剂构造成在大于80℃的温度下抵抗软化。其它实施方案 可以被描述和/或要求保护。

公开(公告)号：US08896110B2

公开(公告)日：2014-11-25

申请号：US13801882

申请日：2013-03-13

申请人： Intel Corporation

发明人： Wei Hu ,  Zhizhong Tang ,  Syadwad Jain ,  Rajen S. Sidhu

IPC分类号： H01L23/02 ,  H01L23/373

CPC分类号： H01L23/3736 ,  H01L23/42 ,  H01L24/33 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2924/01322 ,  H01L2924/16251 ,  H01L2924/00

摘要： Embodiments of the present disclosure describe techniques and configurations for paste thermal interface materials (TIMs) and their use in integrated circuit (IC) packages. In some embodiments, an IC package includes an IC component, a heat spreader, and a paste TIM disposed between the die and the heat spreader. The paste TIM may include particles of a metal material distributed through a matrix material, and may have a bond line thickness, after curing, of between approximately 20 microns and approximately 100 microns. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了用于糊状热界面材料（TIM）的技术和配置及其在集成电路（IC）封装中的应用。 在一些实施例中，IC封装包括设置在管芯和散热器之间的IC部件，散热器和粘合剂TIM。 糊料TIM可以包括通过基质材料分布的金属材料的颗粒，并且在固化后可以具有在约20微米和约100微米之间的粘合线厚度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08809181B2

公开(公告)日：2014-08-19

申请号：US13670687

申请日：2012-11-07

申请人： Intel Corporation

发明人： Rajen S. Sidhu ,  Wei Hu ,  Carl L. Deppisch ,  Martha A. Dudek

IPC分类号： H01L21/44

CPC分类号： H01L24/14 ,  B23K35/0222 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/22 ,  B23K35/26 ,  B23K35/262 ,  B23K35/30 ,  B23K35/3006 ,  B23K35/302 ,  B23K35/36 ,  B23K35/3612 ,  B23K35/3613 ,  B23K35/362 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/14505 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及用于集成电路（IC）封装组件的多焊接技术和配置。 在一个实施例中，一种方法包括在封装衬底的多个焊盘上沉积多个焊球，所述多个焊球对应于所述多个焊盘并且执行焊料回流工艺以在所述多个焊料之间形成焊接点 球和多个垫。 多个焊球的单个焊球包括第一焊料材料和第二焊料材料，第一焊料材料具有大于焊料回流工艺的峰值温度的液相线温度，第二焊料材料具有液相线温度， 小于焊料回流工艺的峰值温度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10049971B2

公开(公告)日：2018-08-14

申请号：US15478064

申请日：2017-04-03

申请人： Intel Corporation

发明人： Thomas J. De Bonis ,  Lilia May ,  Rajen S. Sidhu ,  Mukul P. Renavikar ,  Ashay A. Dani ,  Edward R. Prack ,  Carl L. Deppisch ,  Anna M. Prakash ,  James C. Matayabas ,  Jason Jieping Zhang ,  Srinivasa R. Aravamudhan ,  Chang Lin

IPC分类号： H01L21/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L23/00

摘要： An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

公开(公告)号：US09461014B2

公开(公告)日：2016-10-04

申请号：US14686177

申请日：2015-04-14

申请人： Intel Corporation

发明人： Sriram Srinivasan ,  Ram S. Viswanath ,  Paul R. Start ,  Rajen S. Sidhu ,  Rajasekaran Swaminathan

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367 ,  H01L23/42

CPC分类号： H01L24/81 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/20105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00

摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.

公开(公告)号：US20160260679A1

公开(公告)日：2016-09-08

申请号：US14430131

申请日：2014-03-27

申请人： Intel Corporation

发明人： Kabirkumar J. Mirpuri ,  Hongjin Jiang ,  Tyler N. Osborn ,  Rajen S. Sidhu ,  Ibrahim Bekar ,  Susheel G. Jadhav

IPC分类号： H01L23/00

CPC分类号： H01L24/73 ,  H01L21/4867 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/0569 ,  H01L2224/11 ,  H01L2224/13014 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/29026 ,  H01L2224/29109 ,  H01L2224/29113 ,  H01L2224/73104 ,  H01L2224/92143 ,  H01L2924/014

摘要： Apparatuses, processes, and systems related to an interconnect with an increased z-height and decreased reflow temperature are described herein. In embodiments, an interconnect may include a solder ball and a solder paste to couple the solder ball to a substrate. The solder ball and/or solder paste may be comprised of an alloy with a relatively low melting point and an alloy with a relatively high melting point.

摘要翻译： 这里描述了与具有增加的z高度和降低的回流温度的互连相关的装置，工艺和系统。 在实施例中，互连可以包括焊球和焊膏以将焊球耦合到衬底。 焊球和/或焊膏可以由具有较低熔点的合金和具有较高熔点的合金构成。

公开(公告)号：US09257405B2

公开(公告)日：2016-02-09

申请号：US14328599

申请日：2014-07-10

申请人： INTEL CORPORATION

发明人： Rajen S. Sidhu ,  Wei Hu ,  Carl L. Deppisch ,  Martha A. Dudek

IPC分类号： H01L23/12 ,  H01L23/00 ,  B23K35/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC分类号： H01L24/14 ,  B23K35/0222 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/22 ,  B23K35/26 ,  B23K35/262 ,  B23K35/30 ,  B23K35/3006 ,  B23K35/302 ,  B23K35/36 ,  B23K35/3612 ,  B23K35/3613 ,  B23K35/362 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/14505 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及用于集成电路（IC）封装组件的多焊接技术和配置。 在一个实施例中，一种方法包括在封装衬底的多个焊盘上沉积多个焊球，所述多个焊球对应于所述多个焊盘并且执行焊料回流工艺以在所述多个焊料之间形成焊接点 球和多个垫。 多个焊球的单个焊球包括第一焊料材料和第二焊料材料，第一焊料材料具有大于焊料回流工艺的峰值温度的液相线温度，第二焊料材料具有液相线温度， 小于焊料回流工艺的峰值温度。 可以描述和/或要求保护其他实施例。