公开(公告)号：US11742215B2

公开(公告)日：2023-08-29

申请号：US17386699

申请日：2021-07-28

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Alexander Breymesser ,  Bernhard Goller ,  Matthias Kuenle ,  Helmut Oefner ,  Francisco Javier Santos Rodriguez ,  Stephan Voss

IPC: H01L21/324 ,  H01L21/78 ,  H01L21/265

CPC classification number: H01L21/3247 ,  H01L21/26506 ,  H01L21/7806

Abstract: A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050° C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.

公开(公告)号：US10410911B2

公开(公告)日：2019-09-10

申请号：US15833781

申请日：2017-12-06

Applicant: Infineon Technologies AG

Inventor： Carsten Schaeffer ,  Andreas Moser ,  Matthias Kuenle ,  Matteo Dainese ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/739 ,  H01L21/8234 ,  H01L27/12 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.

公开(公告)号：US12018369B2

公开(公告)日：2024-06-25

申请号：US17370386

申请日：2021-07-08

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Olaf Fiedler ,  Thomas Huber ,  Christian Illemann ,  Mathias Male

IPC: C23C16/455 ,  C23C16/458 ,  C23C16/46

CPC classification number: C23C16/455 ,  C23C16/45504 ,  C23C16/45563 ,  C23C16/45591 ,  C23C16/4585 ,  C23C16/46

Abstract: A processing chamber includes a chamber body, a substrate support configured to hold a substrate in place, and a pre-heat ring having a central opening sized to be disposed around the substrate. A process gas inlet is configured to direct process gas in a lateral direction to flow over the pre-heat ring and the substrate. A process gas flow deflector includes a radially outer mounting portion and a radially inner blade-shaped process gas deflection portion extending in a radial direction. The radially inner blade-shaped process gas deflection portion is shaped as a ring segment. The radially inner blade-shaped process gas deflection portion is disposed above the process gas inlet and dimensioned to overlap with the pre-heat ring, wherein a degree of overlap between the pre-heat ring and process gas flow deflector in the radial direction is at least ½ of the radial dimension of the pre-heat ring.

公开(公告)号：US20190148217A1

公开(公告)日：2019-05-16

申请号：US16192277

申请日：2018-11-15

Applicant: Infineon Technologies AG

Inventor： Andreas Moser ,  Matteo Dainese ,  Matthias Kuenle ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/02 ,  H01L21/78

Abstract: An embodiment of a method for manufacturing a semiconductor device includes: providing a monocrystalline semiconductor substrate having a first side; forming a plurality of recess structures in the semiconductor substrate at the first side; filling the recess structures with a dielectric material to form dielectric islands in the recess structures; forming a semiconductor layer on the first side of the semiconductor substrate to cover the dielectric islands; and subjecting the semiconductor layer to heat treatment and recrystallizing the semiconductor layer to form a recrystallized semiconductor layer, so that a crystal structure of the recrystallized semiconductor layer adapts to a crystal structure of the semiconductor substrate, and so that the semiconductor substrate and the semiconductor layer together form a compound wafer with the dielectric islands at least partially buried in the semiconductor material of the compound wafer.

公开(公告)号：US20190078211A1

公开(公告)日：2019-03-14

申请号：US15700232

申请日：2017-09-11

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Johannes Baumgartl ,  Manfred Engelhardt ,  Christian Illemann ,  Francisco Javier Santos Rodriguez ,  Olaf Storbeck

IPC: C23C16/54 ,  C23C16/02 ,  C23C16/455 ,  H01L21/02

Abstract: A CVD reactor, including a deposition chamber housing a first susceptor and a second susceptor, the first susceptor having a cavity for receiving a first substrate, the first substrate having a front surface and a back surface, the second susceptor having a cavity for receiving a second substrate, the second substrate having a front surface and a back surface, and the first susceptor and the second susceptor are disposed so that the front surface of the first substrate is opposite to the front surface of the second substrate thereby forming a portion of a gas flow channel.

公开(公告)号：US10186587B2

公开(公告)日：2019-01-22

申请号：US15634259

申请日：2017-06-27

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Daniel Schloegl ,  Hans-Joachim Schulze ,  Christoph Weiss

IPC: H01L29/36 ,  H01L29/78 ,  H01L29/739 ,  H01L29/861 ,  H01L29/10 ,  H01L29/08 ,  H01L21/265 ,  H01L29/66

Abstract: A power semiconductor device has a semiconductor body configured to conduct a load current in parallel to an extension direction between first and second load terminals of the power semiconductor device. The semiconductor body includes a doped contact region electrically connected to the second load terminal, a doped drift region having a dopant concentration that is smaller than a dopant concentration of the contact region, and an epitaxially grown doped transition region separated from the second load terminal by the contact region and that couples the contact region to the drift region. An upper subregion of the transition region is in contact with the drift region, and a lower subregion of the transition region is in contact with the contact region. The transition region has a dopant concentration of at least 0.5*1015 cm−3 for at least 5% of the total extension of the transition region in the extension direction.

公开(公告)号：US20170373157A1

公开(公告)日：2017-12-28

申请号：US15634259

申请日：2017-06-27

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Daniel Schloegl ,  Hans-Joachim Schulze ,  Christoph Weiss

IPC: H01L29/36 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L29/861 ,  H01L29/739

CPC classification number: H01L29/36 ,  H01L21/265 ,  H01L29/0804 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66325 ,  H01L29/66674 ,  H01L29/66712 ,  H01L29/7393 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/861

Abstract: A power semiconductor device has a semiconductor body configured to conduct a load current in parallel to an extension direction between first and second load terminals of the power semiconductor device. The semiconductor body includes a doped contact region electrically connected to the second load terminal, a doped drift region having a dopant concentration that is smaller than a dopant concentration of the contact region, and an epitaxially grown doped transition region separated from the second load terminal by the contact region and that couples the contact region to the drift region. An upper subregion of the transition region is in contact with the drift region, and a lower subregion of the transition region is in contact with the contact region. The transition region has a dopant concentration of at least 0.5*1015 cm−3 for at least 5% of the total extension of the transition region in the extension direction.

公开(公告)号：US20160322472A1

公开(公告)日：2016-11-03

申请号：US15142992

申请日：2016-04-29

Applicant: Infineon Technologies AG

Inventor： Daniel Schloegl ,  Johannes Baumgartl ,  Matthias Kuenle ,  Erwin Lercher ,  Hans-Joachim Schulze ,  Christoph Weiss

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L29/06 ,  H01L21/02 ,  H01L21/283 ,  H01L29/739 ,  H01L29/08

CPC classification number: H01L29/7395 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/265 ,  H01L21/266 ,  H01L21/283 ,  H01L29/0634 ,  H01L29/0688 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/6609 ,  H01L29/66204 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/861 ,  H01L29/868

Abstract: A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn). Epitaxially growing the drift layer includes creating, within the drift layer, a dopant concentration profile (P) of dopants of the first conductivity type along the vertical direction (Z), the dopant concentration profile (P) in the drift layer exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction (Z).

Abstract translation: 提出了一种制造半导体器件的方法。 该方法包括：提供具有表面的半导体衬底; 沿着垂直于表面的垂直方向（Z）外延生长，在表面顶部具有背面发射极层，其中背面发射极层具有第一导电类型的掺杂剂或与第一导电类型互补的第二导电类型的掺杂剂 导电型; 沿着垂直方向（Z）外延生长具有位于背侧发射极层之上的第一导电类型的掺杂剂的漂移层，其中背面发射极层的掺杂剂浓度高于漂移层的掺杂剂浓度; 并且在所述漂移层的内部或之上产生具有所述第二导电类型的掺杂剂的体区，在所述体区和漂移层之间形成pn结（Zpn）的过渡。 外延生长漂移层包括在漂移层内产生沿着垂直方向（Z）的第一导电类型的掺杂剂的掺杂剂浓度分布（P），漂移层中的掺杂剂浓度分布（P）表现出 沿着垂直方向（Z）的第一导电类型的掺杂剂的浓度。

公开(公告)号：US20140335700A1

公开(公告)日：2014-11-13

申请号：US13892003

申请日：2013-05-10

Applicant: Infineon Technologies AG

Inventor： Guenter Denifl ,  Markus Kahn ,  Helmut Schoenherr ,  Daniel Maurer ,  Thomas Grille ,  Joachim Hirschler ,  Ursula Hedenig ,  Roland Moennich ,  Matthias Kuenle

IPC: H01L21/02 ,  C23C16/26

CPC classification number: H01L21/02115 ,  C23C16/26 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02263 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362

Abstract: Carbon layers with reduced hydrogen content may be deposited by plasma-enhanced chemical vapor deposition by selecting processing parameters accordingly. Such carbon layers may be subjected to high temperature processing without showing excessive shrinking.

Abstract translation: 通过选择相应的处理参数，可以通过等离子体增强化学气相沉积来沉积具有降低的氢含量的碳层。 这样的碳层可以经受高温处理而不会显着过度收缩。

公开(公告)号：US20230395394A1

公开(公告)日：2023-12-07

申请号：US18236434

申请日：2023-08-22

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Alexander Breymesser ,  Bernhard Goller ,  Matthias Kuenle ,  Helmut Oefner ,  Francisco Javier Santos Rodriguez ,  Stephan Voss

IPC: H01L21/324 ,  H01L21/78 ,  H01L21/265

CPC classification number: H01L21/3247 ,  H01L21/7806 ,  H01L21/26506

Abstract: A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.