公开(公告)号：US11594621B2

公开(公告)日：2023-02-28

申请号：US17087678

申请日：2020-11-03

Applicant: Infineon Technologies AG

Inventor： Antonio Vellei ,  Markus Beninger-Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Alexander Philippou ,  Francisco Javier Santos Rodriguez

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/40 ,  H01L21/033 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.

公开(公告)号：US20180145161A1

公开(公告)日：2018-05-24

申请号：US15858217

申请日：2017-12-29

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Matteo Dainese ,  Peter Lechner ,  Hans-Joachim Schulze ,  Johannes Georg Laven

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/04 ,  H01L29/861

CPC classification number: H01L29/7393 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/8613 ,  H01L2924/13055

Abstract: According to an embodiment of a semiconductor device, the device includes first and second trenches formed in a semiconductor body and an electrode disposed in each of the trenches. One of the electrodes is a gate electrode, and the other electrode is electrically disconnected from the gate electrode. The semiconductor device further includes a semiconductor mesa between the trenches. The semiconductor mesa includes a separation region and at least one of a source region and a body region located in the semiconductor mesa. A drift zone is provided below the at least one of the source region and the body region. In the separation region, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.

公开(公告)号：US09837506B2

公开(公告)日：2017-12-05

申请号：US15422049

申请日：2017-02-01

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Matteo Dainese ,  Peter Lechner ,  Hans-Joachim Schulze ,  Johannes Georg Laven

IPC: H01L21/332 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L21/762 ,  H01L29/40 ,  H01L29/739

CPC classification number: H01L29/66348 ,  H01L21/02238 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0843 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

Abstract: A method of manufacturing a semiconductor device includes forming electrode trenches in a semiconductor substrate between semiconductor mesas that separate the electrode trenches, the semiconductor mesas including portions of a drift layer of a first conductivity type and a body layer of a second, complementary conductivity type between a first surface of the semiconductor substrate and the drift layer, respectively. The method further includes forming isolated source zones of the first conductivity type in the semiconductor mesas, the source zones extending from the first surface into the body layer. The method also includes forming separation structures in the semiconductor mesas between neighboring source zones arranged along an extension direction of the semiconductor mesas, the separation structures forming partial or complete constrictions of the semiconductor mesa, respectively.

公开(公告)号：US09666665B2

公开(公告)日：2017-05-30

申请号：US14248371

申请日：2014-04-09

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Matteo Dainese ,  Peter Lechner

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/739 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08

CPC classification number: H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397

Abstract: A semiconductor device includes a body zone in a semiconductor mesa, which is formed between neighboring control structures that extend from a first surface into a semiconductor body. A drift zone forms a first pn junction with the body zone. In the semiconductor mesa, the drift zone includes a first drift zone section that includes a constricted section of the semiconductor mesa. A minimum horizontal width of the constricted section parallel to the first surface is smaller than a maximum horizontal width of the body zone. An emitter layer between the drift zone and the second surface parallel to the first surface includes at least one first zone of a conductivity type of the drift zone.

公开(公告)号：US09570577B2

公开(公告)日：2017-02-14

申请号：US14275378

申请日：2014-05-12

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Matteo Dainese ,  Peter Lechner ,  Hans-Joachim Schulze ,  Johannes Georg Laven

IPC: H01L21/425 ,  H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/66348 ,  H01L21/02238 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0843 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

Abstract: A semiconductor device includes a semiconductor mesa that includes at least one body zone forming first pn junctions with source zones and a second pn junction with a drift zone. Electrode structures are on opposite sides of the semiconductor mesa. At least one of the electrode structures includes a gate electrode configured to control a charge carrier flow through the at least one body zone. In a separation region between the source zones, which are arranged along an extension direction of the semiconductor mesa, the semiconductor mesa includes at least one partial or complete constriction.

Abstract translation: 半导体器件包括半导体台面，其包括与源极区形成第一pn结的至少一个体区和具有漂移区的第二pn结。 电极结构位于半导体台面的相对侧。 电极结构中的至少一个包括被配置为控制通过至少一个体区的电荷载流子的栅电极。 在沿着半导体台面的延伸方向布置的源区之间的分离区域中，半导体台面包括至少一个部分或完全的收缩。

公开(公告)号：US09281360B1

公开(公告)日：2016-03-08

申请号：US14457491

申请日：2014-08-12

Applicant: Infineon Technologies AG

Inventor： Karin Buchholz ,  Matteo Dainese ,  Elmar Falck ,  Hans-Joachim Schulze ,  Gerhard Schmidt ,  Frank Umbach

IPC: H01L29/02 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A semiconductor device has a semiconductor body including opposing bottom and top sides, a surface surrounding the semiconductor body, an active semiconductor region formed in the semiconductor body, an edge region surrounding the active semiconductor region, a first semiconductor zone of a first conduction type formed in the edge region, an edge termination structure formed in the edge region at the top side, and a shielding structure arranged on that side of the edge termination structure facing away from the bottom side. The shielding structure has a number of N1≧2 first segments and a number of N2≧1 second segments. Each of the first segments is electrically connected to each of the other first segments and to each of the second segments, and each of the second segments has an electric resistivity higher than an electric resistivity of each of the first segments.

Abstract translation: 半导体器件具有半导体本体，该半导体本体包括相对的底部和顶侧，围绕半导体主体的表面，形成在半导体本体中的有源半导体区域，围绕有源半导体区域的边缘区域，形成第一导电类型的第一半导体区域 在边缘区域中，形成在顶侧的边缘区域中的边缘终端结构以及布置在边缘终端结构的背离底侧的那一侧的屏蔽结构。 屏蔽结构具有多个N1≥2个第一段和N 2个≥1个第二段。 每个第一段电连接到每个其它第一段和每个第二段，并且每个第二段具有高于每个第一段的电阻率的电阻率。

公开(公告)号：US09231091B2

公开(公告)日：2016-01-05

申请号：US14275193

申请日：2014-05-12

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Matteo Dainese ,  Peter Lechner ,  Hans-Joachim Schulze ,  Johannes Georg Laven

IPC: H01L29/739 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L29/7393 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/8613 ,  H01L2924/13055

Abstract: A semiconductor device includes a semiconductor mesa with at least one body zone forming first pn junctions with source zones and a second pn junction with a drift zone. A pedestal layer at a side of the drift zone opposite to the at least one body zone includes first zones of a conductivity type of the at least one body zone and second zones of the conductivity type of the drift zone. Electrode structures are on opposite sides of the semiconductor mesa. At least one of the electrode structures includes a gate electrode controlling a charge carrier flow through the at least one body zone. In a separation region between two of the source zones (i) a capacitive coupling between the gate electrode and the semiconductor mesa or (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.

Abstract translation: 半导体器件包括具有与源区形成第一pn结的至少一个体区和具有漂移区的第二pn结的半导体台面。 与漂移区相对的至少一个体区的一侧的基座层包括至少一个体区的导电类型的第一区和漂移区的导电类型的第二区。 电极结构位于半导体台面的相对侧。 电极结构中的至少一个包括控制通过至少一个体区的电荷载流子的栅电极。 在两个源极区（i）之间的分离区域中，栅电极和半导体台面之间的电容耦合或（ii）漂移区的多数电荷载流子的电导率低于分离区的外部。

公开(公告)号：US20240413229A1

公开(公告)日：2024-12-12

申请号：US18808486

申请日：2024-08-19

Applicant: Infineon Technologies AG

Inventor： Christian Philipp Sandow ,  Matteo Dainese

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device is proposed. The semiconductor device includes trenches extending into a semiconductor body from a first main surface. A first group of the trenches includes a gate electrode. A second group of the trenches includes a source electrode, the source electrode being subdivided into at least a first part and a second part. A conductance per unit length of the first part along a longitudinal direction of the source electrode is smaller than a conductance per unit length of the second part along the longitudinal direction of the source electrode, the second part being electrically coupled to a source contact area via the first part. A mesa region bounded by a trench of the first group and a trench of the second group includes a source region electrically connected to the source contact area.

公开(公告)号：US20210313460A1

公开(公告)日：2021-10-07

申请号：US17350505

申请日：2021-06-17

Applicant: Infineon Technologies AG ,  Infineon Technologies Dresden GmbH & Co. KG

Inventor： Matteo Dainese ,  Alexander Philippou ,  Markus Beninger-Bina ,  Ingo Dirnstorfer ,  Erich Griebl ,  Christian Jaeger ,  Johannes Georg Laven ,  Caspar Leendertz ,  Frank Dieter Pfirsch

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

Abstract: A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

公开(公告)号：US20190288094A1

公开(公告)日：2019-09-19

申请号：US16430970

申请日：2019-06-04

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Matteo Dainese ,  Peter Lechner ,  Hans-Joachim Schulze ,  Johannes Georg Laven

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor mesa having source zones arranged along a longitudinal axis of the semiconductor mesa and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. The semiconductor device further includes stripe-shaped electrode structures on opposite sides of the semiconductor mesa and separation regions between neighboring ones of the source zones. At least one of the electrode structures includes a gate electrode. In the separation regions, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation regions.