公开(公告)号：US09368475B2

公开(公告)日：2016-06-14

申请号：US14749644

申请日：2015-06-25

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/768 ,  H01L21/02 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L24/97 ,  H01L21/02304 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/145 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2224/11

Abstract: A manufacturing method of a semiconductor device is provided. First, a mould is provided. The mould has a chamber, patterns in the chamber, and protrusions in the chamber. A carrier substrate having at least one die located thereon is disposed in the chamber, and the protrusions surround the die. A thermosetting material is injected into the chamber and is cured. The cured thermosetting material is separated from the mould, so as to form an interposer substrate. A plurality of through holes corresponding to the protrusions and a plurality of grooves corresponding to the patterns are formed on the interposer substrate. A conductive material is filled into the through holes and the grooves to form a plurality of conductive pillars and a first conductive pattern layer on a first surface of the interposer substrate. The first conductive pattern layer is electrically connected with the conductive pillars.

Abstract translation: 提供一种半导体器件的制造方法。 首先，提供模具。 模具具有腔室，腔室中的图案和腔室中的突起。 具有位于其上的至少一个管芯的载体衬底设置在腔室中，并且突出部围绕模具。 将热固性材料注入室中并固化。 将固化的热固性材料与模具分离，以形成插入物基板。 对应于突起的多个通孔和对应于图案的多个槽形成在插入器基板上。 将导电材料填充到通孔和沟槽中以在内插器基板的第一表面上形成多个导电柱和第一导电图案层。 第一导电图案层与导电柱电连接。

公开(公告)号：US20140346666A1

公开(公告)日：2014-11-27

申请号：US14019548

申请日：2013-09-06

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/4803 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49827 ,  H01L24/81 ,  H01L25/065 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes following steps. A mould is provided. The mould has a chamber and a plurality of protrusions in the chamber. A thermosetting material is injected into the chamber. The thermosetting material is cured. A parting step is performed to separate the cured thermosetting material from the mould, so as to form an interposer substrate. A plurality of blind holes corresponding to the protrusions is formed on the interposer substrate. A conductive material is filled into the blind holes to form a plurality of conductive pillars. A conductive pattern layer is formed on a surface of the interposer substrate. The conductive pattern layer is electrically connected with the conductive pillars.

Abstract translation: 提供了一种半导体器件及其制造方法。 制造方法包括以下步骤。 提供模具。 模具在腔室中具有腔室和多个突起。 将热固性材料注入室中。 热固性材料固化。 执行分离步骤以将固化的热固性材料与模具分离，以形成插入物基板。 在内插基板上形成有与突起对应的多个盲孔。 将导电材料填充到盲孔中以形成多个导电柱。 导电图案层形成在中介层基板的表面上。 导电图案层与导电柱电连接。

公开(公告)号：US10416114B2

公开(公告)日：2019-09-17

申请号：US15352242

申请日：2016-11-15

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jui-Chin Chen ,  Pei-Jer Tzeng ,  Tzu-Kun Ku ,  Yu-Chen Hsin ,  Yiu-Hsiang Chang

IPC: G01N27/403 ,  G01N27/417 ,  G01N33/483 ,  G01N33/487 ,  G01N27/27 ,  G01N27/327

Abstract: A structure of an electrochemical unit includes a substrate, a first metal layer disposed on the substrate, and an array of electrochemical cells disposed on the first metal layer. The array of the electrochemical cells includes a plurality of electrochemical cells. Each of the electrochemical cells includes the first metal layer disposed on the substrate, a first electrode disposed on the first metal layer, a polymer layer disposed on the substrate and adjacent to the first metal layer and the first electrode. A second metal layer is disposed on the polymer layer, and a second electrode is disposed on the second metal layer. A pore is constituted between the polymer layers of every the two electrochemical cells. A cavity located above the first electrode is defined between every the two electrochemical cells, wherein the cavity is communicated with the pore.

公开(公告)号：US09093312B2

公开(公告)日：2015-07-28

申请号：US14019548

申请日：2013-09-06

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L23/04 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L24/11 ,  H01L21/4803 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49827 ,  H01L24/81 ,  H01L25/065 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes following steps. A mold is provided. The mold has a chamber and a plurality of protrusions in the chamber. A thermosetting material is injected into the chamber. The thermosetting material is cured. A parting step is performed to separate the cured thermosetting material from the mold, so as to form an interposer substrate. A plurality of blind holes corresponding to the protrusions is formed on the interposer substrate. A conductive material is filled into the blind holes to form a plurality of conductive pillars. A conductive pattern layer is formed on a surface of the interposer substrate. The conductive pattern layer is electrically connected with the conductive pillars.

Abstract translation: 提供了一种半导体器件及其制造方法。 制造方法包括以下步骤。 提供模具。 模具在腔室中具有腔室和多个突起。 将热固性材料注入室中。 热固性材料固化。 执行分离步骤以将固化的热固性材料与模具分离，以形成插入物基板。 在内插基板上形成有与突起对应的多个盲孔。 将导电材料填充到盲孔中以形成多个导电柱。 导电图案层形成在中介层基板的表面上。 导电图案层与导电柱电连接。

公开(公告)号：US09257338B2

公开(公告)日：2016-02-09

申请号：US14615922

申请日：2015-02-06

Applicant: Industrial Technology Research Institute

Inventor： Chung-Chih Wang ,  Pei-Jer Tzeng ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/321 ,  H01L21/3213 ,  H01L25/00

CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/562 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/81 ,  H01L2224/8114 ,  H01L2224/81911 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

Abstract translation: 本公开提供TSV衬底结构和多个衬底结构的层叠组件，TSV衬底结构包括：衬底，其包括第一表面，相应的第二表面以及将第一表面与第二表面通过第二表面连通的TSV 基质; 以及完全填充TSV的导体单元，所述导体单元包括分别具有对应于所述基板的第一和第二表面的第一端和第二端的导体本体。

公开(公告)号：US20150294953A1

公开(公告)日：2015-10-15

申请号：US14749644

申请日：2015-06-25

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/56 ,  H01L25/065 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00 ,  H01L21/768 ,  H01L21/48

CPC classification number: H01L24/97 ,  H01L21/02304 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/145 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2224/11

Abstract: A manufacturing method of a semiconductor device is provided. First, a mould is provided. The mould has a chamber, patterns in the chamber, and protrusions in the chamber. A carrier substrate having at least one die located thereon is disposed in the chamber, and the protrusions surround the die. A thermosetting material is injected into the chamber and is cured. The cured thermosetting material is separated from the mould, so as to form an interposer substrate. A plurality of through holes corresponding to the protrusions and a plurality of grooves corresponding to the patterns are formed on the interposer substrate. A conductive material is filled into the through holes and the grooves to form a plurality of conductive pillars and a first conductive pattern layer on a first surface of the interposer substrate. The first conductive pattern layer is electrically connected with the conductive pillars.

Abstract translation: 提供一种半导体器件的制造方法。 首先，提供模具。 模具具有腔室，腔室中的图案和腔室中的突起。 具有位于其上的至少一个管芯的载体衬底设置在腔室中，并且突出部围绕模具。 将热固性材料注入室中并固化。 将固化的热固性材料与模具分离，以形成插入物基板。 对应于突起的多个通孔和对应于图案的多个槽形成在插入器基板上。 将导电材料填充到通孔和沟槽中以在内插器基板的第一表面上形成多个导电柱和第一导电图案层。 第一导电图案层与导电柱电连接。

公开(公告)号：US20140238725A1

公开(公告)日：2014-08-28

申请号：US13778132

申请日：2013-02-27

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Erh-Hao Chen ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H05K1/02 ,  H05K3/26

CPC classification number: H05K3/107 ,  H05K3/045 ,  H05K3/247 ,  H05K2201/0376 ,  H05K2203/025

Abstract: A method of flattening surface of conductive structure including a substrate, a dielectric layer on the substrate, and a conductive line formed in the dielectric layer is provided. A surface of the conductive line has a recess. A cover layer is formed on the substrate. A mechanical polishing process is performed to remove a portion of the cover layer. A remaining cover layer fills and levels the recess.

Abstract translation: 提供了包括基板，基板上的电介质层和形成在电介质层中的导电线的导电结构的表面平坦化的方法。 导线的表面具有凹部。 在基板上形成覆盖层。 执行机械抛光工艺以去除覆盖层的一部分。 剩余的覆盖层填充并平整凹部。

公开(公告)号：US20140175655A1

公开(公告)日：2014-06-26

申请号：US13911075

申请日：2013-06-06

Applicant: Industrial Technology Research Institute

Inventor： Jui-Chin Chen ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L21/7684 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05541 ,  H01L2224/05547 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05647 ,  H01L2224/0807 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/11845 ,  H01L2224/1191 ,  H01L2224/16145 ,  H01L2224/80097 ,  H01L2224/80345 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2924/00014

Abstract: A chip bonding structure at least includes a first substrate, a second substrate opposite to the first substrate, and a copper bonding structure sandwiched in between the first and the second substrates. A Cu—Cu bonding interface is within the copper bonding structure and is characterized with combinations of protrusions and recesses, and the copper crystallization orientation at one side of the Cu—Cu bonding interface is different from that at another side.

Abstract translation: 芯片接合结构至少包括第一基板，与第一基板相对的第二基板和夹在第一和第二基板之间的铜接合结构。 Cu-Cu键合界面在铜结合结构内，其特征在于突起和凹陷的组合，Cu-Cu键合界面一侧的铜结晶取向与另一侧不同。