摘要:
A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.
摘要:
A recursive metal-embedded chip assembly (R-MECA) process and method is described for heterogeneous integration of multiple die from diverse device technologies. The recursive aspect of this integration technology enables integration of increasingly-complex subsystems while bridging different scales for devices, interconnects and components. Additionally, the proposed concepts include high thermal management performance that is maintained through the multiple recursive levels of R-MECA, which is a key requirement for high-performance heterogeneous integration of digital, analog mixed signal and RF subsystems. At the wafer-scale, chips from diverse technologies and different thicknesses are initially embedded in a metal heat spreader surrounded by a mesh wafer host. An embodiment uses metal embedding on the backside of the chips as a key differentiator for high-density integration, and built-in thermal management. After die embedding, wafer-level front side interconnects are fabricated to interconnect the various chips and with each other. The wafer is then diced into individual metal-embedded chip assembly (MECA) modules, and forms the level one for multi-scale R-MECA integration. These modules are subsequently integrated into another wafer or board using the same integration approach recursively. Additional components such as discrete passive resistors, capacitors and inductors can be integrated at the second level, once the high-resolution, high-density integration has been performed at level zero. This recursive integration offers a practical solution to build very large scale integrated systems and subsystems.
摘要:
A method of forming an E-plane probe includes forming a plurality of monolithically integrated circuits (MICs) on a wafer, each MIC including a monolithic microwave integrated circuit (MMIC), and an E-plane probe coupled to the MMIC, mounting the wafer on an ultra-violet (UV) tape, cutting the wafer with a laser at a first power and a first linear cutting speed along vertical streets and then along horizontal streets to form separate substrates, cutting with the laser at a second power and a second linear cutting speed a rectangle or a portion of a rectangle from the separate substrates to form narrow substrate extensions on the substrates, and repeating this step for each rectangle or portion of a rectangle to be cut to form substrate extensions, and curing the UV tape, wherein the E-plane probes are on the narrow substrate extensions.
摘要:
Methods using chemical vapor deposition (CVD) of diamond deposited on a sacrificial material provide CVD diamond microchannel structures and 3-D interconnection structures of CVD diamond microfluidic channels. The sacrificial material is patterned to define locations and dimensions of the microchannels. The patterned sacrificial material is selectively removed from underneath the chemical vapor deposited (CVD) diamond to form the CVD diamond microchannels. The CVD diamond microchannels are integrated with electronic structures to provide an integral microfluidic cooling system to electronic devices.
摘要:
An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.
摘要:
A method and apparatus for mounting microelectronic chips to a thermal heat sink. The chips are arranged in a desired configuration with their active faces all facing a common direction and with their active faces defining a common planar surface for all of said chips. A metallic material is applied to the chip, preferably by electroplating to backsides of the chips, the metallic material being electro-formed thereon and making void-free contact with the backsides of the chips.
摘要:
A method of fabricating amplifiers, includes monolithically integrating a field-plate transistor and T-gate transistor on a single wafer. A device includes a monolithically integrated field-plate transistor and T-gate transistor on a single wafer.
摘要:
A method of mounting one or more semiconductor or microelectronic chips, which includes providing a carrier; temporarily adhering the one or more semiconductor or microelectronic chips to the carrier with active faces of the one or more chips facing towards the carrier; providing a package body with at least one chip-receiving opening therein and with at least one contact opening therein; temporarily adhering the package body to the carrier with the at least one opening in the package body accommodating at least a portion of the one or more chips; covering backsides of the one or more chips and filling empty spaces between the one or more chips and walls of the at least one opening in the package body with a metallic material; filling the at least one contact opening with the aforementioned metallic material; wirebonding contacts on the active faces of the one or more chips with contact surfaces in electrical communication with the metallic material in the at least one contact opening; and releasing package body with the one or more chips embedded in the metallic material from the carrier.
摘要:
A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.
摘要:
A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.