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公开(公告)号:US20220140121A1
公开(公告)日:2022-05-05
申请号:US17578996
申请日:2022-01-19
发明人: Hiroshi MIYATA , Seiji NOGUCHI , Souichi YOSHIDA , Hiromitsu TANABE , Kenji KOUNO , Yasushi OKURA
IPC分类号: H01L29/739 , H01L29/08 , H01L29/10 , H01L29/66 , H01L29/423 , H01L21/768 , H01L29/40 , H01L29/06 , H01L29/861 , H01L29/417 , H01L29/45
摘要: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.
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公开(公告)号:US20170373141A1
公开(公告)日:2017-12-28
申请号:US15686216
申请日:2017-08-25
发明人: Souichi YOSHIDA , Seiji NOGUCHI , Kenji KOUNO , Hiromitsu TANABE
IPC分类号: H01L29/06 , H01L29/739 , H01L29/66 , H01L29/40 , H01L29/167 , H01L29/10 , H01L29/08 , H01L27/06 , H01L21/324 , H01L21/265 , H01L21/225 , H01L29/861 , H01L21/22
摘要: A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.
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3.
公开(公告)号:US20170047322A1
公开(公告)日:2017-02-16
申请号:US15337405
申请日:2016-10-28
发明人: Souichi YOSHIDA , Hiroshi MIYATA
IPC分类号: H01L27/06 , H01L29/66 , H01L29/739
CPC分类号: H01L27/0664 , H01L21/28 , H01L27/04 , H01L27/0727 , H01L29/0834 , H01L29/1095 , H01L29/417 , H01L29/6609 , H01L29/66333 , H01L29/739 , H01L29/7395 , H01L29/78 , H01L29/861 , H01L29/8613 , H01L29/868
摘要: A semiconductor device, including a semiconductor substrate, a plurality of trenches formed on a front surface of the semiconductor substrate, a plurality of gate electrodes formed in the trenches, a base region and an anode region formed between adjacent trenches respectively in first and second element regions of the semiconductor substrate, a plurality of emitter regions and contact regions selectively formed in the base region, an interlayer insulating film covering the gate electrodes, first and second contact holes penetrating the interlayer insulating film, a plurality of contact plugs embedded in the first contact holes, a first electrode contacting the contact plugs and contacting the anode region via the second contact hole, a collector region and a cathode region formed on a back surface of the semiconductor substrate respectively in the first and second element regions, and a second electrode contacting the collector region and the cathode region.
摘要翻译: 一种半导体器件,包括半导体衬底,形成在半导体衬底的前表面上的多个沟槽,形成在沟槽中的多个栅极电极,分别形成在第一和第二元件中的相邻沟槽之间的基极区域和阳极区域 半导体衬底的区域,选择性地形成在基极区域中的多个发射极区域和接触区域,覆盖栅电极的层间绝缘膜,穿过层间绝缘膜的第一和第二接触孔,嵌入第一 接触孔,接触接触塞并经由第二接触孔接触阳极区域的第一电极,分别形成在第一和第二元件区域中的半导体衬底的背面上的集电极区域和阴极区域,以及第二电极 使集电极区域和阴极区域接触。
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公开(公告)号:US20160211257A1
公开(公告)日:2016-07-21
申请号:US14960274
申请日:2015-12-04
发明人: Souichi YOSHIDA
IPC分类号: H01L27/06 , H01L29/06 , H01L29/861 , H01L29/739
CPC分类号: H01L29/861 , H01L27/0727 , H01L29/0696 , H01L29/0834 , H01L29/1095 , H01L29/36 , H01L29/407 , H01L29/42368 , H01L29/66136 , H01L29/66348 , H01L29/7397 , H01L29/8613
摘要: In an IGBT portion, a first gate electrode is provided in a first trench via a first gate insulating film. A thickness of a first gate insulating film lower portion is thicker than a thickness of a first gate insulating film upper portion, whereby a width of a mesa portion between adjacent first trenches is narrower at a portion of a collector side than at an emitter side. In a diode portion, a second gate electrode is provided inside a second trench via second gate insulating film. A width of the second trench is uniform along a depth direction or narrows from the emitter side toward the collector side. Widths of the second trench are narrower than a sum of a width of the first trench lower portion and the thickness of the first gate insulating film lower portion of both side walls of the first trench lower portion.
摘要翻译: 在IGBT部分中,第一栅极经由第一栅极绝缘膜设置在第一沟槽中。 第一栅极绝缘膜下部的厚度比第一栅极绝缘膜上部的厚度厚,由此相邻的第一沟槽之间的台面部分的宽度在集电极侧的部分比在发射极侧的部分窄。 在二极管部分中,第二栅电极经由第二栅绝缘膜设置在第二沟槽内。 第二沟槽的宽度沿着深度方向是均匀的,或者从发射极侧向集电极侧变窄。 第二沟槽的宽度比第一沟槽下部的宽度和第一沟槽下部的两个侧壁的第一栅极绝缘膜下部的厚度的和窄。
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5.
公开(公告)号:US20210028019A1
公开(公告)日:2021-01-28
申请号:US17071762
申请日:2020-10-15
发明人: Kouji MUKAI , Souichi YOSHIDA
IPC分类号: H01L21/22 , H01L29/36 , H01L29/66 , H01L27/07 , H01L21/265 , H01L21/324 , H01L27/06 , H01L29/06 , H01L29/08 , H01L29/32 , H01L29/739 , H01L29/861
摘要: Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided.
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公开(公告)号:US20180166549A1
公开(公告)日:2018-06-14
申请号:US15792772
申请日:2017-10-25
发明人: Ryoichi KATO , Hiromichi GOHARA , Takafumi YAMADA , Kohei YAMAUCHI , Tatsuhiko ASAI , Yoshitaka NISHIMURA , Akio KITAMURA , Hajime MASUBUCHI , Souichi YOSHIDA
IPC分类号: H01L29/423 , H01L29/739 , H01L23/28 , H01L23/367
CPC分类号: H01L29/42376 , H01L21/3205 , H01L21/768 , H01L23/28 , H01L23/36 , H01L23/367 , H01L23/3735 , H01L23/50 , H01L24/73 , H01L25/07 , H01L25/18 , H01L29/423 , H01L29/739 , H01L2224/73263
摘要: A semiconductor device including a semiconductor element, an upper-surface electrode provided on an upper surface of the semiconductor element, a plated layer provided on an upper surface of the upper-surface electrode, one or more gate runners penetrating the plated layer and provided to extend in a predetermined direction on the upper surface of the semiconductor element, and a metal connecting plate that is arranged above the plated layer and is electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion that is connected to a first end of the joint portion and extends in a direction away from the upper surface of the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, the rising portion and the gate runner do not overlap with each other.
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公开(公告)号:US20180047725A1
公开(公告)日:2018-02-15
申请号:US15791760
申请日:2017-10-24
发明人: Souichi YOSHIDA , Masaki TAMURA , Kenji KOUNO , Hiromitsu TANABE
IPC分类号: H01L27/07 , H01L29/08 , H01L29/06 , H01L21/8249
CPC分类号: H01L27/0716 , H01L21/8249 , H01L27/0727 , H01L28/20 , H01L29/0696 , H01L29/083 , H01L29/0834 , H01L29/32 , H01L29/407 , H01L29/7397 , H01L29/8611 , H01L29/8613
摘要: On a front surface side of an n− semiconductor substrate, an emitter electrode and trench gates each including a p base layer, a trench, a gate oxide film and a gate electrode are provided in an IGBT region and a FWD region. Among p base layers each between adjacent trenches, p base layers having an n+ emitter region are the IGBT emitter region and the p base layers not having the n+ emitter region are the FWD anode region. A lateral width of an n+ cathode region is narrower than a lateral width of the FWD anode region. A difference of a lateral width of the FWD anode region and a lateral width of the n+ cathode region is 50 μm or more. Thus, a semiconductor device may be provided that reduces the forward voltage drop while suppressing waveform oscillation during reverse recovery and having soft recover characteristics.
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公开(公告)号:US20180012762A1
公开(公告)日:2018-01-11
申请号:US15694116
申请日:2017-09-01
发明人: Kouji MUKAI , Souichi YOSHIDA
IPC分类号: H01L21/22 , H01L29/739 , H01L29/32 , H01L29/08 , H01L29/06 , H01L27/06 , H01L21/324 , H01L29/861 , H01L21/265
CPC分类号: H01L21/221 , H01L21/265 , H01L21/26506 , H01L21/3221 , H01L21/324 , H01L27/0664 , H01L27/0727 , H01L29/0638 , H01L29/0834 , H01L29/32 , H01L29/36 , H01L29/66136 , H01L29/7397 , H01L29/8613
摘要: Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided.
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公开(公告)号:US20160043073A1
公开(公告)日:2016-02-11
申请号:US14882427
申请日:2015-10-13
IPC分类号: H01L27/06 , H01L29/10 , H01L29/06 , H01L29/739
CPC分类号: H01L27/0664 , H01L29/0696 , H01L29/0834 , H01L29/1095 , H01L29/456 , H01L29/66348 , H01L29/7397
摘要: An IGBT is disposed in an IGBT portion, and an FWD is disposed in an FWD portion. A p-type base region and an n−-type drift region are alternately exposed in a trench longitudinal direction in a substrate front surface in a mesa portion between neighboring trenches in the IGBT portion. A p-type anode region and the n−-type drift region are alternately exposed in the trench longitudinal direction in the substrate front surface in a mesa portion in the FWD portion, and a repetitive structure is formed with a portion of the n−-type drift region sandwiched between p-type anode regions and one p-type anode region in contact with the portion as one unit region. The proportion occupied by the p-type anode region in one unit region (an anode ratio) (α) is 50% to 100%.
摘要翻译: IGBT配置在IGBT部,FWD配置在FWD部。 在IGBT部分的相邻沟槽之间的台面部分的衬底前表面中,在沟槽纵向上交替地露出p型基极区域和n型漂移区域。 p型阳极区域和n型漂移区域在FWD部分的台面部分中的衬底前表面中在沟槽纵向方向上交替暴露,并且重复结构形成有n- 类型漂移区域夹在p型阳极区域和一个p型阳极区域之间,该区域与作为一个单位区域的部分接触。 一个单位区域(阳极比)(α)中的p型阳极区域所占的比例为50%〜100%。
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10.
公开(公告)号:US20140070270A1
公开(公告)日:2014-03-13
申请号:US14025321
申请日:2013-09-12
发明人: Souichi YOSHIDA , Toshihito KAMEI , Seiji NOGUCHI
IPC分类号: H01L29/739 , H01L29/66
CPC分类号: H01L29/7395 , H01L29/0696 , H01L29/66128 , H01L29/66348 , H01L29/7397 , H01L29/861 , H01L29/8611
摘要: IGBT and diode are formed with optimal electrical characteristics on the same semiconductor substrate. IGBT region and FWD region are provided on the same semiconductor substrate. There are a plurality of trenches at predetermined intervals in the front surface of an n− type semiconductor substrate, and P-type channel regions at predetermined intervals in the longitudinal direction of the trench between neighboring trenches, thereby configuring a MOS gate. The p-type channel region and n− type drift region are alternately disposed in longitudinal direction of the trench in the IGBT region. The p-type channel region and a p− type spacer region are alternately disposed in the longitudinal direction of the trench in the FWD region. Pitch in longitudinal direction of the trench of p-type channel region in the IGBT region is shorter than pitch in longitudinal direction of the trench of p-type channel region in the FWD region.
摘要翻译: IGBT和二极管在相同的半导体衬底上形成最佳的电气特性。 IGBT区域和FWD区域设置在同一半导体衬底上。 在n型半导体衬底的前表面中以预定间隔存在多个沟槽,并且在相邻沟槽之间的沟槽的纵向方向上以预定间隔设置P型沟道区,从而构成MOS栅极。 p型沟道区域和n型漂移区域在IGBT区域的沟槽的纵向方向上交替设置。 p型沟道区域和p型间隔区域在FWD区域中的沟槽的纵向交替地设置。 IGBT区域中p型沟道区域的沟槽的纵向方向的间距小于FWD区域中p型沟道区域的沟槽的纵向方向的间距。
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