-
公开(公告)号：US09691442B2
公开(公告)日：2017-06-27
申请号：US14667888
申请日：2015-03-25
发明人： Thomas Andre , Syed M. Alam , Dietmar Gogl
CPC分类号： G11C7/02 , G11C5/14 , G11C5/145 , G11C5/146 , G11C5/147 , G11C7/06 , G11C7/1006 , G11C7/18 , G11C8/12 , G11C16/12 , G11C16/30
摘要： In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.
-
公开(公告)号：US09542989B2
公开(公告)日：2017-01-10
申请号：US14887426
申请日：2015-10-20
发明人： Dietmar Gogl , Syed M. Alam , Thomas Andre
CPC分类号： G11C11/1675 , G11C5/147 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1697 , G11C13/0069 , G11C2213/79
摘要： A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
摘要翻译： 电池偏置控制电路通过自动调节存储器阵列上的读/写路径的多个控制输入，使存储器单元（磁隧道结器件+晶体管）的读/写路径中的器件的性能最大化，而不会超过泄漏电流或可靠性限制 根据电源电压，温度和过程角变化的预定义配置，通过将任何特定参考参数配置文件应用于存储器阵列。
-
3.发明授权公开(公告)号：US09418001B2
公开(公告)日：2016-08-16
申请号：US14827628
申请日：2015-08-17
发明人： Syed M. Alam , Thomas Andre , Dietmar Gogl
IPC分类号： G11C11/00 , G06F12/02 , G11C7/10 , G11C11/4076 , G11C8/04 , G06F12/06 , G11C11/16 , G11C11/4094 , G11C11/4096 , G11C14/00
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F2212/205 , G06F2212/7201 , G11C7/1042 , G11C7/1072 , G11C8/04 , G11C11/005 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C14/0036
摘要： A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
摘要翻译： 描述了用于交织易失性和非易失性存储器访问的存储器系统和存储器控制器。 在存储器系统中，存储器控制器使用共享地址总线耦合到易失性和非易失性存储器。 激活易失性和非易失性存储器的延迟是不同的，寄存器包含在存储器控制器中用于存储延迟值。 存储器控制器上的附加寄存器存储存储器的预充电延迟以及非易失性存储器的页面大小。 存储器控制器上的存储器访问定序器向存储器发出适当的片选信号以启动其中的操作。
-
公开(公告)号：US20160019139A1
公开(公告)日：2016-01-21
申请号：US14827628
申请日：2015-08-17
发明人： Syed M. Alam , Thomas Andre , Dietmar Gogl
IPC分类号： G06F12/02 , G11C11/16 , G06F12/06 , G11C11/4096 , G11C7/10 , G11C14/00 , G11C11/4094
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F2212/205 , G06F2212/7201 , G11C7/1042 , G11C7/1072 , G11C8/04 , G11C11/005 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C14/0036
摘要： A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
-
公开(公告)号：US20130308374A1
公开(公告)日：2013-11-21
申请号：US13892107
申请日：2013-05-10
发明人： Dietmar Gogl , Syed M. Alam , Thomas Andre
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C5/147 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1697 , G11C13/0069 , G11C2213/79
摘要： A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
摘要翻译： 电池偏置控制电路通过自动调节存储器阵列上的读/写路径的多个控制输入，使存储器单元（磁隧道结器件+晶体管）的读/写路径中的器件的性能最大化，而不会超过泄漏电流或可靠性限制 根据电源电压，温度和过程角变化的预定义配置，通过将任何特定参考参数配置文件应用于存储器阵列。
-
6.发明申请MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES 审中-公开用于交互DRAM和MRAM访问的存储器控制器和方法公开(公告)号：US20160350031A1
公开(公告)日：2016-12-01
申请号：US15212271
申请日：2016-07-17
发明人： Syed M. Alam , Thomas Andre , Dietmar Gogl
IPC分类号： G06F3/06 , G11C11/4091 , G11C11/4096 , G11C14/00 , G11C11/16
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F2212/205 , G06F2212/7201 , G11C7/1042 , G11C7/1072 , G11C8/04 , G11C11/005 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C14/0036
摘要： A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
摘要翻译： 描述了用于交织易失性和非易失性存储器访问的存储器系统和存储器控制器。 在存储器系统中，存储器控制器使用共享地址总线耦合到易失性和非易失性存储器。 激活易失性和非易失性存储器的延迟是不同的，寄存器包含在存储器控制器中用于存储延迟值。 存储器控制器上的附加寄存器存储存储器的预充电延迟以及非易失性存储器的页面大小。 存储器控制器上的存储器访问定序器向存储器发出适当的片选信号以启动其中的操作。
-
7.发明申请BOOSTED SUPPLY VOLTAGE GENERATOR FOR A MEMORY DEVICE AND METHOD THEREFORE 审中-公开用于存储器件的升压电源电压发生器及其方法公开(公告)号：US20160172019A1
公开(公告)日：2016-06-16
申请号：US15051794
申请日：2016-02-24
发明人： Dietmar Gogl , Syed M. Alam , Thomas Andre , Halbert S. Lin
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C8/08 , G11C11/1657 , G11C11/1693 , G11C11/1697
摘要： A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.
摘要翻译： 升压的电源电压发生器被选择性地激活和去激活，以允许以稳定的升压电压来执行对升压电压的变化敏感的操作。 还公开了用于停用和重新激活电压发生器的技术，其使得能够从停用中更快速地恢复，使得可以更快地开始后续操作。 这样的技术包括当停用时存储对应于电压发生器的状态信息，其中在重新激活电压发生器时使用存储的状态信息。 存储状态信息可以包括提供给电压发生器的时钟信号的状态。
-
公开(公告)号：US09183912B2
公开(公告)日：2015-11-10
申请号：US13892107
申请日：2013-05-10
发明人： Dietmar Gogl , Syed M. Alam , Thomas Andre
CPC分类号： G11C11/1675 , G11C5/147 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1697 , G11C13/0069 , G11C2213/79
摘要： A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
摘要翻译： 电池偏置控制电路通过自动调节存储器阵列上的读/写路径的多个控制输入，使存储器单元（磁隧道结器件+晶体管）的读/写路径中的器件的性能最大化，而不会超过泄漏电流或可靠性限制 根据电源电压，温度和过程角变化的预定义配置，通过将任何特定参考参数配置文件应用于存储器阵列。
-
公开(公告)号：US20140104963A1
公开(公告)日：2014-04-17
申请号：US14050625
申请日：2013-10-10
发明人： Thomas Andre , Syed M. Alam , Dietmar Gogl
CPC分类号： G11C7/02 , G11C5/14 , G11C5/145 , G11C5/146 , G11C5/147 , G11C7/06 , G11C7/1006 , G11C7/18 , G11C8/12 , G11C16/12 , G11C16/30
摘要： In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.
摘要翻译： 在一些示例中，存储器件包括配备有隔离开关和专用电源引脚的多个存储体。 每个存储体的隔离开关被配置为将存储体与全局信号隔离。 专用电源引脚被配置为将每个存储器组连接到封装衬底上的专用本地电源焊盘，以向每个存储体提供本地专用电源，并且通过设备上的导体来减少存储体之间的电压传输 ，器件衬底或存储器件的封装衬底。
-
公开(公告)号：US09740431B2
公开(公告)日：2017-08-22
申请号：US15212271
申请日：2016-07-17
发明人： Syed M. Alam , Thomas Andre , Dietmar Gogl
IPC分类号： G11C11/00 , G06F3/06 , G11C7/10 , G11C11/4076 , G11C8/04 , G06F12/02 , G06F12/06 , G11C11/16 , G11C11/4094 , G11C11/4096 , G11C14/00 , G06F13/16 , G11C11/4091
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F2212/205 , G06F2212/7201 , G11C7/1042 , G11C7/1072 , G11C8/04 , G11C11/005 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C14/0036
摘要： A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
-
-
-
-
-
-
-
-
-
搜索结果
20 条记录 (耗时 0.015 秒)
