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    METHOD FOR FORMING 3D-INTERCONNECT STRUCTURES WITH AIRGAPS
    2.
    发明申请
    METHOD FOR FORMING 3D-INTERCONNECT STRUCTURES WITH AIRGAPS 有权
    用于形成3D互连结构的方法

    公开(公告)号：US20120013022A1

    公开(公告)日：2012-01-19

    申请号：US13183315

    申请日：2011-07-14

    申请人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Eric Beyne

    发明人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Eric Beyne

    IPC分类号： H01L23/48 ,  H01L21/28

    CPC分类号： H01L21/76898 ,  H01L21/7682 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

    摘要： Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material.

    摘要翻译： 公开了超低电容互连结构，优选地通过硅通孔（TSV）互连和用于制造所述互连的方法。 该制造方法包括以下步骤：提供具有第一主表面的基底，从第一主表面至少产生一个中空的沟槽状结构，所述沟槽状结构围绕基底材料的内柱结构，沉积介电衬垫 其在第一主表面处夹紧所述中空沟槽状结构，使得在中空沟槽状结构的中心产生气隙，并进一步产生TSV孔并至少部分地用导电材料填充TSV孔。

    METHOD FOR BONDING A DIE OR SUBSTRATE TO A CARRIER
    5.
    发明申请
    METHOD FOR BONDING A DIE OR SUBSTRATE TO A CARRIER 有权
    将一个或多个基板接合到载体上的方法

    公开(公告)号：US20080166525A1

    公开(公告)日：2008-07-10

    申请号：US11963487

    申请日：2007-12-21

    申请人： Bart Swinnen ,  Eric Beyne

    发明人： Bart Swinnen ,  Eric Beyne

    IPC分类号： B32B37/26 ,  B32B7/06 ,  B44C1/22 ,  B05D7/24

    CPC分类号： H01L21/6835 ,  H01L2221/6834 ,  Y10T428/24 ,  Y10T428/24628

    摘要： A method is disclosed for bonding two elements by means of a bonding agent such as a glue layer, wherein the bonding agent is removable, and wherein between the bonding agent and at least one element, a sacrificial layer is applied which is selectively removable with respect to that element. According to embodiments, the elements comprise a die or a substrate bonded to a carrier wafer. The nature and type of the die or substrate and of the carrier can vary within the scope of embodiments of the invention. Also disclosed is a composite substrate obtainable by methods of the invention.

    摘要翻译： 公开了一种通过诸如胶层之类的粘结剂粘接两个元件的方法，其中粘合剂是可去除的，并且其中在粘合剂和至少一个元件之间施加牺牲层，该牺牲层可相对于 到那个元素 根据实施例，元件包括结合到载体晶片的管芯或衬底。 模具或基底和载体的性质和类型可以在本发明的实施例的范围内变化。 还公开了可通过本发明的方法获得的复合基材。

    Method for chip singulation
    7.
    发明申请
    Method for chip singulation 有权

    公开(公告)号：US20060068567A1

    公开(公告)日：2006-03-30

    申请号：US11234835

    申请日：2005-09-23

    申请人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

    发明人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

    IPC分类号： H01L21/78

    CPC分类号： H01L21/78 ,  H01L21/3043

    摘要： The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

    Method for transferring and stacking of semiconductor devices
    8.
    发明授权
    Method for transferring and stacking of semiconductor devices 有权
    半导体器件的传输和堆叠方法

    公开(公告)号：US06576505B2

    公开(公告)日：2003-06-10

    申请号：US09772195

    申请日：2001-01-29

    申请人： Staf Borghs ,  Eric Beyne ,  Raf Vandersmissen

    发明人： Staf Borghs ,  Eric Beyne ,  Raf Vandersmissen

    IPC分类号： H01L21338

    CPC分类号： H01L21/6835 ,  H01L23/66 ,  H01L31/18 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/00

    摘要： A method is presented in which an active element, e.g. a semiconductor device, is embedded in a passive circuitry formed on a low-cost substrate, having good dielectric properties. After forming the active element on a first substrate, the active elements are singulated and transferred to a second substrate. The active element is bonded to this second substrate and the portion of the first substrate, on which this active element is created, is removed selectively to the active element and the low-cost substrate. On this second substrate passive circuitry may be present or it can be formed after the attachment of the active element. The passive circuitry is interconnected to the active element or other components or dies present on the low-cost substrate.

    摘要翻译： 提出了一种方法，其中有源元件例如 半导体器件被嵌入在低成本衬底上形成的无源电路中，具有良好的介电特性。 在第一衬底上形成有源元件之后，将有源元件分离并转移到第二衬底。 有源元件被结合到该第二衬底，并且在其上产生该有源元件的第一衬底的部分被选择性地去除到有源元件和低成本衬底。 在该第二基板上可以存在无源电路，或者可以在有源元件的附着之后形成无源电路。 无源电路与存在于低成本衬底上的有源元件或其他元件或裸片互连。

    Method for detecting embedded voids in a semiconductor substrate
    10.
    发明授权
    Method for detecting embedded voids in a semiconductor substrate 有权
    用于检测半导体衬底中的嵌入孔的方法

    公开(公告)号：US08735182B2

    公开(公告)日：2014-05-27

    申请号：US13490828

    申请日：2012-06-07

    申请人： Leonardus Leunissen ,  Sandip Halder ,  Eric Beyne

    发明人： Leonardus Leunissen ,  Sandip Halder ,  Eric Beyne

    IPC分类号： H01L21/66 ,  H01L21/00

    CPC分类号： H01L22/12 ,  H01L21/2885 ,  H01L21/76882 ,  H01L21/76883 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for detecting embedded voids present in a structure formed in or on a semiconductor substrate is described. The method includes performing a processing step P1 for forming the structure; measuring the mass M1 of the substrate; performing thermal treatment; measuring the mass M2 of the substrate; calculating the mass difference between the mass of the substrate measured before and after the performed thermal treatment; and deducing the presence of embedded voids in the structure by comparing the mass difference with a pre-determined value.

    摘要翻译： 描述了一种用于检测存在于形成于半导体衬底中的结构中的嵌入孔的方法。 该方法包括执行用于形成该结构的处理步骤P1; 测量衬底的质量M1; 进行热处理; 测量衬底的质量M2; 计算在进行的热处理之前和之后测量的基底的质量差之间的质量差; 并通过将质量差与预定值进行比较，推断结构中嵌入的空隙的存在。