公开(公告)号：US20080166525A1

公开(公告)日：2008-07-10

申请号：US11963487

申请日：2007-12-21

申请人： Bart Swinnen ,  Eric Beyne

发明人： Bart Swinnen ,  Eric Beyne

IPC分类号： B32B37/26 ,  B32B7/06 ,  B44C1/22 ,  B05D7/24

CPC分类号： H01L21/6835 ,  H01L2221/6834 ,  Y10T428/24 ,  Y10T428/24628

摘要： A method is disclosed for bonding two elements by means of a bonding agent such as a glue layer, wherein the bonding agent is removable, and wherein between the bonding agent and at least one element, a sacrificial layer is applied which is selectively removable with respect to that element. According to embodiments, the elements comprise a die or a substrate bonded to a carrier wafer. The nature and type of the die or substrate and of the carrier can vary within the scope of embodiments of the invention. Also disclosed is a composite substrate obtainable by methods of the invention.

摘要翻译： 公开了一种通过诸如胶层之类的粘结剂粘接两个元件的方法，其中粘合剂是可去除的，并且其中在粘合剂和至少一个元件之间施加牺牲层，该牺牲层可相对于 到那个元素 根据实施例，元件包括结合到载体晶片的管芯或衬底。 模具或基底和载体的性质和类型可以在本发明的实施例的范围内变化。 还公开了可通过本发明的方法获得的复合基材。

公开(公告)号：US20060068567A1

公开(公告)日：2006-03-30

申请号：US11234835

申请日：2005-09-23

申请人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

发明人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/3043

摘要： The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

公开(公告)号：US08809188B2

公开(公告)日：2014-08-19

申请号：US12885311

申请日：2010-09-17

申请人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Bart Swinnen ,  Eric Beyne

发明人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Bart Swinnen ,  Eric Beyne

IPC分类号： H01L21/44

CPC分类号： H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

摘要翻译： 公开了一种通过衬底通孔制造的方法。 在一个方面，通孔从衬底的背面蚀刻到浅沟槽隔离（STI）或预金属电介质叠层（PMD）。 制造金属1接触焊盘和贯通晶片通孔之间的额外接触，以实现贯穿晶片通孔和半导体芯片的后端行之间的接触。

公开(公告)号：US20110089572A1

公开(公告)日：2011-04-21

申请号：US12885311

申请日：2010-09-17

申请人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Bart Swinnen ,  Eric Beyne

发明人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Bart Swinnen ,  Eric Beyne

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

摘要翻译： 公开了一种通过衬底通孔制造的方法。 在一个方面，通孔从衬底的背面蚀刻到浅沟槽隔离（STI）或预金属电介质叠层（PMD）。 制造金属1接触焊盘和贯通晶片通孔之间的额外接触，以实现贯穿晶片通孔和半导体芯片的后端行之间的接触。

公开(公告)号：US07795113B2

公开(公告)日：2010-09-14

申请号：US11963487

申请日：2007-12-21

申请人： Bart Swinnen ,  Eric Beyne

发明人： Bart Swinnen ,  Eric Beyne

IPC分类号： H01L21/46

CPC分类号： H01L21/6835 ,  H01L2221/6834 ,  Y10T428/24 ,  Y10T428/24628

摘要： A method is disclosed for bonding two elements by means of a bonding agent such as a glue layer, wherein the bonding agent is removable, and wherein between the bonding agent and at least one element, a sacrificial layer is applied which is selectively removable with respect to that element. According to embodiments, the elements comprise a die or a substrate bonded to a carrier wafer. The nature and type of the die or substrate and of the carrier can vary within the scope of embodiments of the invention. Also disclosed is a composite substrate obtainable by methods of the invention.

摘要翻译： 公开了一种通过诸如胶层之类的粘结剂粘接两个元件的方法，其中粘合剂是可去除的，并且其中在粘合剂和至少一个元件之间施加牺牲层，该牺牲层可相对于 到那个元素 根据实施例，元件包括结合到载体晶片的管芯或衬底。 模具或基底和载体的性质和类型可以在本发明的实施例的范围内变化。 还公开了可通过本发明的方法获得的复合基材。

公开(公告)号：US07566634B2

公开(公告)日：2009-07-28

申请号：US11234835

申请日：2005-09-23

申请人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

发明人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/3043

摘要： The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

摘要翻译： 本发明涉及一种用于从诸如晶片或基板上的层的层叠单片化芯片的方法。 层叠层包括在衬底层上的前端（FEOL）层，衬底层具有第一表面和第二表面。 FEOL位于第一表面的顶部，并且后端（BEOL）层位于FEOL的顶部。 该方法包括通过BEOL，通过FEOL蚀刻单个沟槽并且至少部分地穿过衬底层，在设置有单个沟槽的堆叠上沉积钝化层，由此蚀刻的单个化沟槽的侧壁至少部分钝化。 执行切割，例如刀片切割，激光切割或沟槽蚀刻切割，从堆叠层释放芯片。

公开(公告)号：US20100261310A1

公开(公告)日：2010-10-14

申请号：US12822000

申请日：2010-06-23

申请人： Kenneth Kaskoun ,  Shiqun Gu ,  Bart Swinnen

发明人： Kenneth Kaskoun ,  Shiqun Gu ,  Bart Swinnen

IPC分类号： H01L21/50 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/06181 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.

摘要翻译： 多层IC器件包含第一裸片，其包括具有第一组和第二组通孔的衬底。 第一组通孔从衬底的一侧延伸，并且第二组通孔从衬底的相对侧延伸。 两组通孔耦合在一起。 第一组通孔在物理上小于第二组通孔。 第一组通孔在芯片上的电路之前产生，并且第二组通孔在芯片上的电路之后产生。 具有一组互连件的第二管芯相对于第一管芯堆叠，其中互连件耦合到第一组通孔。

公开(公告)号：US07939926B2

公开(公告)日：2011-05-10

申请号：US12334433

申请日：2008-12-12

申请人： Kenneth Kaskoun ,  Shiqun Gu ,  Bart Swinnen

发明人： Kenneth Kaskoun ,  Shiqun Gu ,  Bart Swinnen

IPC分类号： H01L23/02

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/06181 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.

摘要翻译： 多层IC器件包含第一裸片，其包括具有第一组和第二组通孔的衬底。 第一组通孔从衬底的一侧延伸，并且第二组通孔从衬底的相对侧延伸。 两组通孔耦合在一起。 第一组通孔在物理上小于第二组通孔。 第一组通孔在芯片上的电路之前产生，并且第二组通孔在芯片上的电路之后产生。 具有一组互连件的第二管芯相对于第一管芯堆叠，其中互连件耦合到第一组通孔。

公开(公告)号：US20060103822A1

公开(公告)日：2006-05-18

申请号：US10990335

申请日：2004-11-17

申请人： Roy Werkman ,  Franciscus Van Bilsen ,  Bart Swinnen

发明人： Roy Werkman ,  Franciscus Van Bilsen ,  Bart Swinnen

IPC分类号： G03B27/52

CPC分类号： G03F7/70633 ,  G03F9/7046

摘要： The invention relates to a method of optimizing an alignment strategy for processing batches of substrates in a lithographic projection apparatus. First, all substrates in a plurality of batches of substrates in the lithographic projection apparatus are sequentially aligned and exposed using a predefined alignment strategy. Then, alignment data is determined for each substrate in the plurality of batches of substrates. Next, at least one substrate in each batch of substrates is selected to render a set of selected substrates comprising at least one substrate in each batch. In a metrology tool, overlay data for each of the selected substrates is determined. Then, overlay indicator values for a predefined overlay indicator are calculated for the predefined alignment strategy and for other possible alignment strategies. In this calculation, the alignment data and the overlay data of the selected substrates is used. Finally, an optimal alignment strategy is determined, the strategy being defined as alignment strategy among the predefined alignment strategy and the other possible alignment strategies with a lowest overlay indicator value.

摘要翻译： 本发明涉及一种优化用于在光刻投影设备中处理批次的基板的对准策略的方法。 首先，光刻投影设备中的多批基板中的所有基板使用预定义的对准策略顺序对准和曝光。 然后，确定多批基板中的每个基板的对准数据。 接下来，选择每批衬底中的至少一个衬底，以在每批中提供包含至少一个衬底的一组选定衬底。 在计量工具中，确定每个所选择的基底的覆盖数据。 然后，为预定义的对齐策略和其他可能的对准策略计算预定义重叠指示符的覆盖指示符值。 在该计算中，使用所选择的基板的对准数据和覆盖数据。 最后，确定最佳对准策略，该策略被定义为预定义对准策略中的对准策略和具有最低覆盖指标值的其他可能的对准策略。

公开(公告)号：US07042552B1

公开(公告)日：2006-05-09

申请号：US10990335

申请日：2004-11-17

申请人： Roy Werkman ,  Franciscus Bernardus Maria Van Bilsen ,  Bart Swinnen

发明人： Roy Werkman ,  Franciscus Bernardus Maria Van Bilsen ,  Bart Swinnen

IPC分类号： G03B27/52 ,  G03B27/42

CPC分类号： G03F7/70633 ,  G03F9/7046

摘要： The invention relates to a method of optimizing an alignment strategy for processing batches of substrates in a lithographic projection apparatus. First, all substrates in a plurality of batches of substrates in the lithographic projection apparatus are sequentially aligned and exposed using a predefined alignment strategy. Then, alignment data is determined for each substrate in the plurality of batches of substrates. Next, at least one substrate in each batch of substrates is selected to render a set of selected substrates including at least one substrate in each batch. In a metrology tool, overlay data for each of the selected substrates is determined. Then, overlay indicator values for a predefined overlay indicator are calculated for the predefined alignment strategy and for other possible alignment strategies. In this calculation, the alignment data and the overlay data of the selected substrates is used. Finally, an optimal alignment strategy is determined, the strategy being defined as alignment strategy among the predefined alignment strategy and the other possible alignment strategies with a lowest overlay indicator value.

摘要翻译： 本发明涉及一种优化用于在光刻投影设备中处理批次的基板的对准策略的方法。 首先，光刻投影设备中的多批基板中的所有基板使用预定义的对准策略顺序对准和曝光。 然后，确定多批基板中的每个基板的对准数据。 接下来，选择每批衬底中的至少一个衬底，以在每批中提供包括至少一个衬底的一组选定衬底。 在计量工具中，确定每个所选择的基底的覆盖数据。 然后，为预定义的对齐策略和其他可能的对准策略计算预定义重叠指示符的覆盖指示符值。 在该计算中，使用所选择的基板的对准数据和覆盖数据。 最后，确定最佳对准策略，该策略被定义为预定义对准策略中的对准策略和具有最低覆盖指标值的其他可能的对准策略。