Method for fabricating a semiconductor device including using a hard mask or a silylated photoresist for an angled tilted ion implant
    1.
    发明授权
    Method for fabricating a semiconductor device including using a hard mask or a silylated photoresist for an angled tilted ion implant 有权
    用于制造半导体器件的方法,包括使用硬掩模或甲硅烷基化光致抗蚀剂用于倾斜倾斜离子注入

    公开(公告)号:US06821830B2

    公开(公告)日:2004-11-23

    申请号:US10647284

    申请日:2003-08-26

    IPC分类号: H01L21338

    摘要: A hard mask 21a which has an opening for exposing a p-type region 2 defined in a silicon substrate 1 and is made of, for example, a BPSG film is formed. Then, the hard mask 21a is subjected to isotropic etching using argon gas, to have its edge rounded off, thereby forming an implantation hard mask 21 having a tapered edge. Subsequently, large-angle-tilt ion implantation of an n-type impurity is performed using the implantation hard mask 21 as a mask, thereby forming an n− layer 13 having an LDD structure. Thereafter, the implantation hard mask 11 is removed. In this manner, it is possible to perform large-angle-tilt ion implantation using an implantation mask thinner than a conventional implantation mask.

    摘要翻译: 形成具有用于露出硅基板1中限定的并由例如BPSG膜制成的p型区域2的开口的硬掩模21a。 然后,使用氩气对硬掩模21a进行各向同性蚀刻,使其边缘倒圆,从而形成具有锥形边缘的注入硬掩模21。 随后,使用注入硬掩模21作为掩模进行n型杂质的大角度倾斜离子注入,从而形成具有LDD结构的n层13。 此后,移除注入硬掩模11。 以这种方式,可以使用比常规植入掩模更薄的注入掩模进行大角度倾斜离子注入。

    Quantum well detector with layer for the storage of photo-excited electrons
    2.
    发明授权
    Quantum well detector with layer for the storage of photo-excited electrons 失效
    量子阱检测器用于存储光电子的层

    公开(公告)号:US06809350B1

    公开(公告)日:2004-10-26

    申请号:US09328391

    申请日:1999-06-09

    IPC分类号: H01L21338

    CPC分类号: H01L31/0352

    摘要: A quantum well made out of a the stack of layers of III-V semiconductor materials comprises, in addition to the quantum well, an electron storage layer separated from the quantum well by a transfer barrier layer. The barrier layer has a thickness that is greater than the thickness of the quantum well by about one order of magnitude. This barrier thus enables the separation of the absorption function (in the quantum well) and the function of reading the photocarriers (in the storage layer) and therefore the limiting of the rate of recombination of the carriers, thus improving the performance characteristics of the detector.

    摘要翻译: 由III-V族半导体材料层构成的量子阱除量子阱之外还包括通过转移阻挡层与量子阱分离的电子存储层。 阻挡层的厚度大于量子阱的厚度大约一个数量级。 因此,该障碍物能够分离吸收功能(在量子阱中)和读取光载体(在存储层中)的功能,因此限制载体的复合速率,从而提高检测器的性能特征 。

    Method of fabricating a MOS transistor with a drain extension and corresponding transistor
    3.
    发明授权
    Method of fabricating a MOS transistor with a drain extension and corresponding transistor 有权
    制造具有漏极延伸的MOS晶体管和对应的晶体管的方法

    公开(公告)号:US06800514B2

    公开(公告)日:2004-10-05

    申请号:US10184036

    申请日:2002-06-27

    IPC分类号: H01L21338

    CPC分类号: H01L29/66659 H01L29/7835

    摘要: A MOS transistor with a drain extension includes an isolation block on the upper surface of a semiconductor substrate. The isolation block has a first sidewall next to the gate of the transistor, and a second sidewall that is substantially parallel to the first sidewall. The isolation block further includes a drain extension zone in the substrate under the isolation block, and a drain region in contact with the drain extension zone. The drain region is in the substrate but is not covered by the isolation block.

    摘要翻译: 具有漏极延伸的MOS晶体管包括在半导体衬底的上表面上的隔离块。 隔离块具有靠近晶体管的栅极的第一侧壁和基本上平行于第一侧壁的第二侧壁。 隔离块还包括在隔离块下方的衬底中的漏极延伸区域和与漏极延伸区域接触的漏极区域。 漏极区在衬底中,但不被隔离块覆盖。

    Method for making semiconductor device
    4.
    发明授权
    Method for making semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号:US06784036B2

    公开(公告)日:2004-08-31

    申请号:US10456493

    申请日:2003-06-09

    IPC分类号: H01L21338

    摘要: A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding over an undercut in an underlying layer, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.

    摘要翻译: 制造半导体器件的方法包括通过执行多个显影步骤形成具有多层结构的抗蚀剂图案,所述抗蚀剂图案包括对应于栅电极的精细栅极部分的第一开口和位于所述栅电极上的第二开口 第一开口,第二开口对应于比精细门部分更宽的横截面部分,并且具有在下层中的底切上突出的横截面,其中在过门顶端处的第二开口的每个角度 截面超过90度; 以及通过在抗蚀剂图案上沉积电极材料来形成设置有精细栅极部分和栅极极化部分的栅电极。

    Low-K gate spacers by fluorine implantation
    6.
    发明授权
    Low-K gate spacers by fluorine implantation 有权
    通过氟注入的低K栅间隔

    公开(公告)号:US06720213B1

    公开(公告)日:2004-04-13

    申请号:US10345344

    申请日:2003-01-15

    IPC分类号: H01L21338

    摘要: A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.

    摘要翻译: MOSFET器件和制造具有通过氟注入产生的低K电介质氧化物栅极侧壁间隔物的MOSFET器件的方法。 本发明将氟注入到栅极氧化物侧壁间隔物中,其用于改变高级复合栅极电介质的性质,例如, 氮化的氧化物,NO和栅极侧壁电介质,使得氟的低K特性用于开发低寄生电容MOSFET。

    Fabricating a substantially self-aligned MOSFET
    7.
    发明授权
    Fabricating a substantially self-aligned MOSFET 失效
    制造基本上自对准的MOSFET

    公开(公告)号:US06649460B2

    公开(公告)日:2003-11-18

    申请号:US10028523

    申请日:2001-10-25

    IPC分类号: H01L21338

    摘要: The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (such as a first polysilicon) having horizontal surfaces and also having opposed vertical surfaces forming a trench; providing a second material (such as a second polysilicon) in the trench and over the vertical and horizontal surfaces, the second material having a substantially (eg, ±10%) uniform thickness so as to form a notch over the trench; providing a masking material (such as an oxide or a nitride) into the notch, and then removing the second material using the masking material as a mask in a direction toward the first material, so that a vertical surface of one of the first materials is at least substantially aligned with a vertical surface of the second material.

    摘要翻译: 本发明包括用于形成至少基本自对准MOSFET的方法和结构。 根据本发明,制造半导体器件的方法包括提供衬底; 提供具有水平表面的第一材料(例如第一多晶硅),并且还具有形成沟槽的相对的垂直表面; 在沟槽中并在垂直和水平表面上提供第二材料(例如第二多晶硅),第二材料具有基本上(例如±10%)均匀的厚度,以便在沟槽上形成切口; 在凹口中提供掩模材料(例如氧化物或氮化物),然后使用掩模材料作为掩模在朝向第一材料的方向上去除第二材料,使得第一材料之一的垂直表面为 至少基本上与第二材料的垂直表面对准。

    Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same
    8.
    发明授权
    Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same 有权
    具有沉积栅极电介质和金属栅电极的硅锗MOSFET及其制造方法

    公开(公告)号:US06620664B2

    公开(公告)日:2003-09-16

    申请号:US10072248

    申请日:2002-02-07

    IPC分类号: H01L21338

    CPC分类号: H01L29/66916 H01L29/802

    摘要: An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

    摘要翻译: 集成电路金属氧化物半导体器件包括位于其中的栅极区域和电介质层,其中介电层基本上不含有从器件的硅锗层扩散的锗。 该方法包括沉积虚拟置换栅极,对器件进行高温处理,去除伪栅极,然后在所形成的栅极区域内沉积介电材料和最终栅极材料。 因为在器件的高温处理之后沉积介电材料,所以锗可以扩散到电介质材料中。

    Semiconductor integrated circuit device and method for manufacturing the same
    9.
    发明授权
    Semiconductor integrated circuit device and method for manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号:US06593229B1

    公开(公告)日:2003-07-15

    申请号:US09635270

    申请日:2000-08-09

    IPC分类号: H01L21338

    摘要: Described is a manufacturing method for a semiconductor integrated circuit device which comprises forming, over a gate insulating film which has been formed over the main surface of a single crystal silicon substrate to have an effective film thickness less than 5 nm in terms of Sio2, a W film as a gate electrode material, and heat treating the silicon substrate in a water-vapor- and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the W film, whereby defects of the gate insulating film rightly under the W film are repaired. According to the present invention, in a MISFET having a metal gate electrode formed over a ultra-thin gate insulating film having an effective film thickness less than 5 nm in terms of SiO2, defects of the gate insulating film can be repaired without oxidizing the metal gate electrode.

    摘要翻译: 描述了一种用于半导体集成电路器件的制造方法,其包括在已经形成在单晶硅衬底的主表面上的栅极绝缘膜上形成以Sio2为单位的有效膜厚度小于5nm的半导体集成电路器件, W膜作为栅电极材料,并且将硅衬底在含有允许硅氧化的比例设定的水蒸气/氢气分压比的水蒸气和氢气气氛中进行热处理,而不会使W膜基本上氧化 由此修复W膜正下方的栅绝缘膜的缺陷。 根据本发明,在具有SiO 2以有效膜厚小于5nm的超薄栅极绝缘膜形成的金属栅电极的MISFET中,可以在不氧化金属的情况下修复栅极绝缘膜的缺陷 栅电极。

    Method of fabricating an insulating layer

    公开(公告)号:US06492214B2

    公开(公告)日:2002-12-10

    申请号:US09683649

    申请日:2002-01-29

    IPC分类号: H01L21338

    CPC分类号: H01L21/28123 H01L21/76224

    摘要: A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.