摘要:
A hard mask 21a which has an opening for exposing a p-type region 2 defined in a silicon substrate 1 and is made of, for example, a BPSG film is formed. Then, the hard mask 21a is subjected to isotropic etching using argon gas, to have its edge rounded off, thereby forming an implantation hard mask 21 having a tapered edge. Subsequently, large-angle-tilt ion implantation of an n-type impurity is performed using the implantation hard mask 21 as a mask, thereby forming an n− layer 13 having an LDD structure. Thereafter, the implantation hard mask 11 is removed. In this manner, it is possible to perform large-angle-tilt ion implantation using an implantation mask thinner than a conventional implantation mask.
摘要:
A quantum well made out of a the stack of layers of III-V semiconductor materials comprises, in addition to the quantum well, an electron storage layer separated from the quantum well by a transfer barrier layer. The barrier layer has a thickness that is greater than the thickness of the quantum well by about one order of magnitude. This barrier thus enables the separation of the absorption function (in the quantum well) and the function of reading the photocarriers (in the storage layer) and therefore the limiting of the rate of recombination of the carriers, thus improving the performance characteristics of the detector.
摘要:
A MOS transistor with a drain extension includes an isolation block on the upper surface of a semiconductor substrate. The isolation block has a first sidewall next to the gate of the transistor, and a second sidewall that is substantially parallel to the first sidewall. The isolation block further includes a drain extension zone in the substrate under the isolation block, and a drain region in contact with the drain extension zone. The drain region is in the substrate but is not covered by the isolation block.
摘要:
A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding over an undercut in an underlying layer, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.
摘要:
A method of producing nitride based heterostructure devices by using a quaternary layer comprised of AlInGaN. The quaternary layer may be used in conjunction with a ternary layer in varying thicknesses and compositions that independently adjust polarization charges and band offsets for device structure optimization by using strain compensation profiles. The profiles can be adjusted by altering profiles of molar fractions of In and Al.
摘要:
A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.
摘要:
The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (such as a first polysilicon) having horizontal surfaces and also having opposed vertical surfaces forming a trench; providing a second material (such as a second polysilicon) in the trench and over the vertical and horizontal surfaces, the second material having a substantially (eg, ±10%) uniform thickness so as to form a notch over the trench; providing a masking material (such as an oxide or a nitride) into the notch, and then removing the second material using the masking material as a mask in a direction toward the first material, so that a vertical surface of one of the first materials is at least substantially aligned with a vertical surface of the second material.
摘要:
An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.
摘要:
Described is a manufacturing method for a semiconductor integrated circuit device which comprises forming, over a gate insulating film which has been formed over the main surface of a single crystal silicon substrate to have an effective film thickness less than 5 nm in terms of Sio2, a W film as a gate electrode material, and heat treating the silicon substrate in a water-vapor- and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the W film, whereby defects of the gate insulating film rightly under the W film are repaired. According to the present invention, in a MISFET having a metal gate electrode formed over a ultra-thin gate insulating film having an effective film thickness less than 5 nm in terms of SiO2, defects of the gate insulating film can be repaired without oxidizing the metal gate electrode.
摘要:
A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.