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公开(公告)号：US06746902B2
公开(公告)日：2004-06-08
申请号：US10062319
申请日：2002-01-31
IPC分类号： H01L2100
CPC分类号： H01L21/322 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02694 , Y10S438/933
摘要： A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 22%, by molecular weight; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.
摘要翻译： 形成Ge含量较高的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的Ge含量通过分子量等于或大于22％; 以约20keV至45keV之间的能量以约1.10 16 cm -2至5.10 16 cm -2的剂量将H +离子注入SiGe层; 热处理基板和SiGe层，以在约650℃至950℃的温度的惰性气氛中放松SiGe层约30秒至30分钟; 以及在弛豫的SiGe层上沉积拉伸应变硅层至约5nm至30nm的厚度。
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2.发明授权Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation 失效STI形成后Si1-xGex CMOS与Si1-xGex弛豫过程的整合公开(公告)号：US06583000B1
公开(公告)日：2003-06-24
申请号：US10072183
申请日：2002-02-07
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/76224 , H01L21/823878
摘要： A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below the SiGe layer; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.
摘要翻译： 形成CMOS器件的方法包括制备硅衬底，包括在衬底上形成多个器件区域; 在衬底上外延地形成应变SiGe层，其中SiGe层的锗含量在约20％和40％之间; 在SiGe层上外延地形成硅帽层; 沉积栅氧化层; 沉积第一多晶硅层; 将H +离子注入SiGe层以下的深度; 通过延伸到衬底中的浅沟槽隔离形成沟槽; 在约700℃至900℃的温度下退火结构约5分钟至60分钟; 沉积氧化物层和第二多晶硅层，从而填充沟槽; 将结构平面化到位于沟槽中的第二多晶硅层的部分的顶部的顶部; 并完成CMOS设备。
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公开(公告)号：US07226504B2
公开(公告)日：2007-06-05
申请号：US10062336
申请日：2002-01-31
申请人： Jer-Shen Maa , Douglas James Tweet , Tingkai Li , Jong-Jan Lee , Sheng Teng Hsu
发明人： Jer-Shen Maa , Douglas James Tweet , Tingkai Li , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： C30B33/02
CPC分类号： H01L21/3247 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02694 , H01L21/324
摘要： A method of forming a SiGe layer having a relatively high germanium content and a relatively low threading dislocation density includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the germanium content of the SiGe layer is greater than 20%, by atomic ratio; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; patterning the SiGe layer with photoresist; plasma etching the structure to form trenches about regions; removing the photoresist; and thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes.
摘要翻译： 形成具有较高锗含量和较低穿透位错密度的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的锗含量按原子比大于20％; 将H +离子以约1.10×16cm -2至0.0010±0.2cm的剂量注入SiGe层中， SUP>，在约20keV至45keV之间的能量; 用光致抗蚀剂图案化SiGe层; 等离子体蚀刻结构以形成关于区域的沟槽; 去除光致抗蚀剂; 以及对基板和SiGe层进行热退火，以在惰性气氛中在约650℃至950℃的温度下放置SiGe层约30秒至30分钟。
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公开(公告)号：US20080303072A1
公开(公告)日：2008-12-11
申请号：US12178169
申请日：2008-07-23
IPC分类号： H01L31/113
CPC分类号： H01L27/14647
摘要： A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.
摘要翻译： CMOS有源像素传感器包括具有在其上形成有绝缘体层的硅衬底和形成在绝缘体层上的顶部硅层的绝缘体上硅衬底。 层叠像素传感器单元包括：制造在硅衬底上的底部光电二极管，用于感测最长波长的光; 制造在硅衬底上的中间光电二极管，用于感测中等波长的光; 和制造在顶部硅层上的顶部光电二极管，用于感测较短波长的光，该光被层叠在中间和底部光电二极管的上方。 像素晶体管组被制造在顶部硅层上，并且通过在每个光电二极管和相应的像素晶体管之间延伸的电连接与每个像素传感器单元相关联。 CMOS控制电路与有源像素传感器单元的阵列相邻并且与其电连接。
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公开(公告)号：US06627919B2
公开(公告)日：2003-09-30
申请号：US10319312
申请日：2002-12-12
IPC分类号： H01L2976
CPC分类号： H01L21/28525 , H01L21/28518 , H01L29/45
摘要： A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800° C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i.e., the resistance remains low when annealing temperatures extend up to and beyond 800° C.
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公开(公告)号：US06194310B1
公开(公告)日：2001-02-27
申请号：US09585680
申请日：2000-06-01
IPC分类号： H01L214763
CPC分类号： H01L21/76864 , H01L21/28556 , H01L2221/1078
摘要： A method of forming conducting diffusion barriers is provided. The method produces substantially amorphous conducting diffusion barriers by depositing materials with varying ratios of elements throughout the diffusion barrier. Diffusion barriers of metal nitride, metal silicon nitride, are deposited using CVD, PECVD, or ALCVD, by depositing material with a first ratio of elements and then depositing substantially identical material with a different ratio of elements. The actual elements used are the same, but the ratio is changed. By changing the ratio of the elements within the same diffusion barrier, density variations are produced, and the material is not able to form undesirable polycrystalline structures.
摘要翻译： 提供形成导电扩散阻挡层的方法。 该方法通过在整个扩散阻挡层中沉积具有不同比例的元素的材料来产生基本上非晶的导电扩散阻挡层。 使用CVD，PECVD或ALCVD沉积金属氮化物，金属氮化硅的扩散屏障，通过以第一比例的元素沉积材料，然后沉积具有不同比例元素的基本相同的材料。 使用的实际元素是相同的，但是比例是改变的。 通过改变相同扩散阻挡层内的元素的比例，产生密度变化，并且材料不能形成不期望的多晶结构。
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7.发明授权Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same 有权具有沉积栅极电介质和金属栅电极的硅锗MOSFET及其制造方法公开(公告)号：US06620664B2
公开(公告)日：2003-09-16
申请号：US10072248
申请日：2002-02-07
IPC分类号： H01L21338
CPC分类号： H01L29/66916 , H01L29/802
摘要： An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.
摘要翻译： 集成电路金属氧化物半导体器件包括位于其中的栅极区域和电介质层，其中介电层基本上不含有从器件的硅锗层扩散的锗。 该方法包括沉积虚拟置换栅极，对器件进行高温处理，去除伪栅极，然后在所形成的栅极区域内沉积介电材料和最终栅极材料。 因为在器件的高温处理之后沉积介电材料，所以锗可以扩散到电介质材料中。
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8.发明授权Method of fabricating high performance SiGe heterojunction bipolar transistor BiCMOS on a silicon-on-insulator substrate 失效在绝缘体上硅衬底上制造高性能SiGe异质结双极晶体管BiCMOS的方法公开(公告)号：US06555874B1
公开(公告)日：2003-04-29
申请号：US09649380
申请日：2000-08-28
IPC分类号： H01L310392
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7378
摘要： A semiconductor structure includes, on a SOI substrate, a CMOS formed on the substrate; and a SiGe HBT formed on the substrate. A method of fabricating a semiconductor structure includes preparing a SOI substrate having plural active regions thereon; forming a CMOS on the SOI substrate in a first active region; and forming a SiGe HBT on the SOI substrate in another active region.
摘要翻译： 半导体结构在SOI衬底上包括在衬底上形成的CMOS; 和形成在衬底上的SiGe HBT。 制造半导体结构的方法包括制备其上具有多个有源区的SOI衬底; 在第一有源区中在SOI衬底上形成CMOS; 以及在另一有源区的SOI衬底上形成SiGe HBT。
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公开(公告)号：US07800148B2
公开(公告)日：2010-09-21
申请号：US12178169
申请日：2008-07-23
IPC分类号： H01L31/062
CPC分类号： H01L27/14647
摘要： A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.
摘要翻译： CMOS有源像素传感器包括具有在其上形成有绝缘体层的硅衬底和形成在绝缘体层上的顶部硅层的绝缘体上硅衬底。 层叠像素传感器单元包括：制造在硅衬底上的底部光电二极管，用于感测最长波长的光; 制造在硅衬底上的中间光电二极管，用于感测中等波长的光; 和制造在顶部硅层上的顶部光电二极管，用于感测较短波长的光，该光被层叠在中间和底部光电二极管的上方。 像素晶体管组被制造在顶部硅层上，并且通过在每个光电二极管和相应的像素晶体管之间延伸的电连接与每个像素传感器单元相关联。 CMOS控制电路与有源像素传感器单元的阵列相邻并且与其电连接。
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公开(公告)号：US06759695B2
公开(公告)日：2004-07-06
申请号：US10661429
申请日：2003-09-11
IPC分类号： H01L29788
CPC分类号： H01L29/66916 , H01L29/802
摘要： An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.
摘要翻译： 集成电路金属氧化物半导体器件包括位于其中的栅极区域和电介质层，其中介电层基本上不含有从器件的硅锗层扩散的锗。 该方法包括沉积虚拟置换栅极，对器件进行高温处理，去除伪栅极，然后在所形成的栅极区域内沉积介电材料和最终栅极材料。 因为在器件的高温处理之后沉积介电材料，所以锗可以扩散到电介质材料中。
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