公开(公告)号：US06777711B2

公开(公告)日：2004-08-17

申请号：US10390014

申请日：2003-03-18

Applicant: Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

Inventor： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

IPC: H01L310392

Abstract: An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

公开(公告)号：US06759712B2

公开(公告)日：2004-07-06

申请号：US10243180

申请日：2002-09-12

Applicant: Arup Bhattacharyya

Inventor： Arup Bhattacharyya

IPC: H01L310392

CPC classification number: H01L29/78696 ,  H01L21/84 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/1203 ,  H01L29/66742 ,  H01L29/78687 ,  Y10S438/933

Abstract: The invention includes SOI thin film transistor constructions, memory devices, computer systems, and methods of forming various structures, devices and systems. The structures typically comprise a thin crystalline layer of silicon/germanium formed over a wide range of suitable substrates. The crystalline properties of the silicon/germanium can be controlled during formation of the silicon/germanium so that the material has a relaxed crystalline lattice and large crystalline grain sizes. The crystalline grain sizes can be sufficiently large so that transistor devices formed in association with the thin crystalline material have active regions utilizing only a single grain of the silicon/germanium material. The silicon/germanium material having a relaxed crystalline lattice can be utilized alone in forming channel regions of transistor devices, or alternatively a semiconductor material having a strained crystalline lattice can be provided between the relaxed crystalline lattice and gates of the transistor devices.

Abstract translation: 本发明包括SOI薄膜晶体管结构，存储器件，计算机系统以及形成各种结构，器件和系统的方法。 结构通常包括在宽范围的合适基底上形成的硅/锗的薄晶体层。 可以在形成硅/锗期间控制硅/锗的晶体性质，使得该材料具有松弛的晶格和大的晶粒尺寸。 晶粒尺寸可以足够大，使得与薄晶体材料相关联地形成的晶体管器件具有仅利用单个晶粒的硅/锗材料的活性区域。 具有松弛晶格的硅/锗材料可以单独用于形成晶体管器件的沟道区，或者可以在晶体管器件的松弛晶格和栅极之间提供具有应变晶格的半导体材料。

公开(公告)号：US06531738B1

公开(公告)日：2003-03-11

申请号：US09651759

申请日：2000-08-30

Applicant: Yasuhiro Uemoto ,  Katsushige Yamashita ,  Takashi Miura

Inventor： Yasuhiro Uemoto ,  Katsushige Yamashita ,  Takashi Miura

IPC: H01L310392

CPC classification number: H01L29/7812 ,  H01L21/76286 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78606 ,  H01L29/78624 ,  H01L29/78654 ,  H01L29/8611

Abstract: In an SOI (Silicon On Insulator) semiconductor device, a first semiconductor layer overlies a semiconductor substrate so as to sandwich an insulating layer, and second and third semiconductor layers with a different conductivity type from the second semiconductor layer are formed on the surface of the first semiconductor layer. At the interface between the first semiconductor layer and the insulating layer, a fourth semiconductor layer with a different conductivity type from the first semiconductor layer is formed. The fourth semiconductor layer includes an impurity of larger than 3×1012/cm2 so as not to be completely depleted even though a reverse bias voltage is applied between the second and third semiconductor layers.

Abstract translation: 在SOI（绝缘体上硅）半导体器件中，第一半导体层覆盖在半导体衬底上以夹住绝缘层，并且在第二半导体层的表面上形成具有与第二半导体层不同的导电类型的第二和第三半导体层 第一半导体层。 在第一半导体层和绝缘层之间的界面处，形成具有与第一半导体层不同的导电类型的第四半导体层。 第四半导体层包括大于3×10 12 / cm 2的杂质，即使在第二和第三半导体层之间施加反向偏置电压也不会完全耗尽。

公开(公告)号：US06278156B1

公开(公告)日：2001-08-21

申请号：US09191389

申请日：1998-11-12

Applicant: Kenya Kobayashi

Inventor： Kenya Kobayashi

IPC: H01L310392

CPC classification number: H01L21/76281 ,  H01L21/76275 ,  H01L21/76283 ,  H01L29/7835

Abstract: An SOI substrate is formed by bonding first and second semiconductor substrates of p− type through an insulating film interposed in between the substrates. In an SOI layer of a p type at the surface side of the two, a trench isolation region is formed for selecting elements so as to enclose an element forming region by burying a trench made of an oxide film. A MOS transistor having p+ type drain diffusion layer and p− type drain diffusion layer is formed in this element forming region isolated by a dielectric region. A same potential is applied to an electrode connected to the p+ diffusion layer provided outside of the element forming region enclosed by the trench isolation region, and the drain diffusion layer. As a result, without forming an electrode on the back side of the SOI substrate, deterioration of withstand voltage of elements can be prevented.

Abstract translation: 通过将介于基板之间的绝缘膜接合p型的第一和第二半导体衬底而形成SOI衬底。 在两个表面侧的p型SOI层中，形成用于选择元件的沟槽隔离区，以便通过埋入由氧化膜制成的沟槽来包围元件形成区域。 在由电介质区域隔离的元件形成区域中形成具有p +型漏极扩散层和p型漏极扩散层的MOS晶体管。 与设置在由沟槽隔离区域包围的元件形成区域外部的p +扩散层连接的电极和漏极扩散层也施加相同的电位。 结果，在SOI衬底的背侧不形成电极，可以防止元件的耐受电压劣化。

公开(公告)号：US06828632B2

公开(公告)日：2004-12-07

申请号：US10197978

申请日：2002-07-18

Applicant: Arup Bhattacharyya

Inventor： Arup Bhattacharyya

IPC: H01L310392

CPC classification number: H01L29/66916 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/78615 ,  H01L29/78687 ,  H01L29/806

Abstract: One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a silicon germanium (Si—Ge) layer. In various embodiments, the well region includes a number of recombination centers between the Si—Ge layer and the insulation layer. A source region, a drain region, a gate oxide layer, and a gate are formed. In various embodiments, the Si—Ge layer includes a number of recombination centers in the source/drain regions. In various embodiments, a metal silicide layer and a lateral metal Schottky layer are formed above the well region to contact the source region and the well region. Other aspects are provided herein.

Abstract translation: 本主题的一个方面涉及部分耗尽的绝缘体上硅结构。 该结构包括形成在氧化物绝缘层之上的阱区。 在各种实施例中，阱区是包括硅锗（Si-Ge）层的多层外延。 在各种实施例中，阱区包括在Si-Ge层和绝缘层之间的多个复合中心。 形成源极区域，漏极区域，栅极氧化物层和栅极。 在各种实施例中，Si-Ge层在源极/漏极区域中包括多个复合中心。 在各种实施例中，金属硅化物层和侧向金属肖特基层形成在阱区上方以接触源区和阱区。 本文提供了其他方面。

公开(公告)号：US06809381B2

公开(公告)日：2004-10-26

申请号：US10059125

申请日：2002-01-31

Applicant: Masahiro Yoshida

Inventor： Masahiro Yoshida

IPC: H01L310392

CPC classification number: H01L29/78615 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

Abstract: A simiconductor device includes a simiconductor substrate, an insulating layer, a silicon layer, full depletion type transistors, and partial deletion type transistors. The insulating layer is formed on the simiconductor substrate. The silicon layer has a first region and a second region. The silicon layer is formed on the insulating layer. The full depletion type transistors are used for a logical circuit and are formed on the silicon layer at the first region. The partial depletion type transistors are used for a memory cell circuit and are formed on the silicon layer at the second region. The second region of the silicon layer is maintained at a fixed potential.

Abstract translation: 一个模拟器件包括一个半导体衬底，一个绝缘层，一个硅层，全部耗尽型晶体管和一个部分缺失型晶体管。 在该三导体基板上形成绝缘层。 硅层具有第一区域和第二区域。 硅层形成在绝缘层上。 全耗尽型晶体管用于逻辑电路，并且在第一区域的硅层上形成。 部分耗尽型晶体管用于存储单元电路，并且形成在第二区域的硅层上。 硅层的第二区域保持固定电位。

公开(公告)号：US06734501B2

公开(公告)日：2004-05-11

申请号：US10058221

申请日：2002-01-29

Applicant: Takuo Sugano ,  Toru Toyabe ,  Tatsuro Hanajiri ,  Akira Saito ,  Yoshiro Akagi

Inventor： Takuo Sugano ,  Toru Toyabe ,  Tatsuro Hanajiri ,  Akira Saito ,  Yoshiro Akagi

IPC: H01L310392

CPC classification number: H01L29/78696 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/66621 ,  H01L29/66772

Abstract: A fully inverted type SOI-MOSFET has a channel region 18 constructed of a portion that belongs to a top silicon layer 13 and is located just under a gate electrode 15 and a source region 16 and a drain region 17, which belong to the top silicon layer 13 and are located adjacent to this channel region 18. The channel region 18 is inverted throughout the entire thickness during operation. The source region 16 has a source resistance RS, which satisfies a relation that (1/gm)>RS with respect to the mutual conductance gm of the channel region 18 itself. According to this fully inverted type SOI-MOSFET, the effective mutual conductance (Gm) can be increased.

Abstract translation: 全反相型SOI-MOSFET具有由属于顶部硅层13的部分构成的沟道区18，该沟道区18位于栅电极15的下方，源极区16和漏极区17属于顶部硅 层13并且位于该通道区域18附近。在操作期间，通道区域18在整个厚度上反转。 源极区域16具有源极电阻RS，其满足关于通道区域18本身的互导体gm的关系（1 / gm）> RS。 根据这种完全反转型的SOI-MOSFET，可以提高有效的互导（Gm）。

公开(公告)号：US06545319B2

公开(公告)日：2003-04-08

申请号：US10023398

申请日：2001-12-13

Applicant: Steven C. Deane ,  Ian D. French

Inventor： Steven C. Deane ,  Ian D. French

IPC: H01L310392

CPC classification number: H01L29/78669 ,  H01L29/41733

Abstract: An insulated-gate thin film transistor comprises a gate electrode and source and drain electrodes. The source and drain electrodes are laterally spaced apart, and are vertically separated from the gate electrode by a gate insulator layer and an amorphous silicon layer. A region of the amorphous silicon layer is vertically aligned with the lateral spacing between the source and drain electrodes defining the transistor channel, and the region of the amorphous silicon layer has a thickness of less than 100 nm, and is doped with phosphorus atoms with a doping density of between 2.5×1016 and 1.5×1018 atoms per cm3. This enables the mobility to be increased so that the thickness reduction of the silicon layer can be tolerated. This thickness reduction enables the photosensitivity of the layer to be reduced sufficiently to avoid the need for a black mask layer.

Abstract translation: 绝缘栅薄膜晶体管包括栅电极和源极和漏极。 源极和漏极横向间隔开，并且通过栅极绝缘体层和非晶硅层与栅电极垂直分离。 非晶硅层的区域与限定晶体管沟道的源极和漏极之间的横向间隔垂直对准，并且非晶硅层的区域具有小于100nm的厚度，并且掺杂有磷原子 掺杂密度在2.5×10 16和1.5×10 18原子/ cm 3之间。 这使得能够增加迁移率，从而可以容忍硅层的厚度减小。 这种厚度减小使得能够充分降低层的光敏性，以避免需要黑色掩模层。

公开(公告)号：US06255695B1

公开(公告)日：2001-07-03

申请号：US08936472

申请日：1997-09-18

Applicant: Yasushi Kubota ,  Kenichi Katoh ,  Jun Koyama

Inventor： Yasushi Kubota ,  Kenichi Katoh ,  Jun Koyama

IPC: H01L310392

CPC classification number: H01L27/1222 ,  H01L27/1214 ,  H01L29/41733

Abstract: In a field-effect transistor, one of the distance between a gate electrode and a source electrode and the distance between the gate electrode and a drain electrode which one distance is on a side where a signal of a high frequency is applied is made longer than the other distance on a side where a signal of a low frequency is applied.

Abstract translation: 在场效应晶体管中，使栅电极与源极之间的距离与施加高频信号的一侧之间的栅电极与漏电极之间的距离长于 施加低频信号的一侧的另一距离。

公开(公告)号：US06835982B2

公开(公告)日：2004-12-28

申请号：US10183888

申请日：2002-06-27

Applicant: Michiru Hogyoku

Inventor： Michiru Hogyoku

IPC: H01L310392

CPC classification number: H01L29/66772 ,  H01L29/7841 ,  H01L29/78615

Abstract: A SOI MOSFET 10 may be formed from silicon single crystal as a substrate body that is formed on an embedded oxide film 11. For example, a P-type body 12, a channel section 13, and N-type source region 14 and drain region 15 are formed therein. Low concentration N-type extension regions 18, a gate electrode 17 provided through a gate dielectric layer 16 and sidewalls 19 are formed therein. A body terminal 101 in which a resistance (body resistance) Rb between itself and a body is positively increased is provided, and the body terminal 101 is connected to a source region 14. This structure realizes a SOI MOSFET with a BTS (Body-Tied-to-Source) operation accompanied by a transient capacitive coupling of a body during a circuit operation.

Abstract translation: 可以由形成在嵌入的氧化膜11上的基板的硅单晶形成SOI MOSFET 10.例如，P型体12，沟道部13，N型源极区14以及漏极区 15。 低浓度N型延伸区域18，通过栅介质层16和侧壁19设置的栅电极17。 提供了其本身和主体之间的电阻（体电阻）Rb正向增加的主体端子101，并且主体端子101连接到源极区域14.该结构实现了具有BTS（体线）的SOI MOSFET 到源）操作，伴随着在电路操作期间身体的瞬时电容耦合。