公开(公告)号：US08497553B2

公开(公告)日：2013-07-30

申请号：US12905801

申请日：2010-10-15

Applicant: Hiroto Yamagiwa ,  Shingo Hashizume ,  Ayanori Ikoshi ,  Manabu Yanagihara ,  Yasuhiro Uemoto

Inventor： Hiroto Yamagiwa ,  Shingo Hashizume ,  Ayanori Ikoshi ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC: H01L23/62 ,  H01L29/66 ,  H01L31/06 ,  H01L21/338 ,  H02H3/00 ,  H02H9/02

CPC classification number: H01L29/7786 ,  H01L27/0266 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/8124 ,  H01L29/861

Abstract: A semiconductor device includes a first transistor formed on a first element region, and a first protecting element including a second transistor formed on a second element region. A second protecting element ohmic electrode is connected to a first gate electrode, a first protecting element ohmic electrode is connected to a first ohmic electrode, and a first protecting element gate electrode is connected to at least one of the first protecting element ohmic electrode and the second protecting element ohmic electrode. The second element region is smaller in area than the first element region.

Abstract translation: 半导体器件包括形成在第一元件区上的第一晶体管和包括形成在第二元件区上的第二晶体管的第一保护元件。 第二保护元件欧姆电极连接到第一栅电极，第一保护元件欧姆电极连接到第一欧姆电极，第一保护元件栅电极连接至第一保护元件欧姆电极和 第二保护元件欧姆电极。 第二元件区域的面积小于第一元件区域。

公开(公告)号：US20120126290A1

公开(公告)日：2012-05-24

申请号：US13360275

申请日：2012-01-27

Applicant: Yasuhiro UEMOTO ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Yasuhiro UEMOTO ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L29/778

CPC classification number: H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7783

Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.

Abstract translation: 氮化物半导体器件包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的带隙的第二氮化物半导体层; 以及形成在所述第二氮化物半导体层上的第三氮化物半导体层。 位于栅电极下方的第三氮化物半导体层的区域形成有具有p型导电性的控制区域，以及位于栅电极与源电极和漏极之间的第三氮化物半导体层的区域 形成有具有比控制区域更高的电阻的高电阻区域。

公开(公告)号：US20110095335A1

公开(公告)日：2011-04-28

申请号：US13001825

申请日：2009-07-02

Applicant: Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Masahiro Hikita

Inventor： Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Masahiro Hikita

IPC: H01L29/06

CPC classification number: H01L29/7787 ,  H01L29/0611 ,  H01L29/0661 ,  H01L29/1029 ,  H01L29/2003

Abstract: A high breakdown voltage GaN-based transistor is provided on a silicon substrate. A nitride semiconductor device including: a silicon substrate, a SiO2 layer stacked on the silicon substrate and having a film thickness 100 nm or more; a silicon layer stacked on the SiO2 layer; a buffer layer stacked on the silicon layer; a GaN layer stacked on the buffer layer; an AlGaN layer stacked on the GaN layer; and a source electrode, a drain electrode, and a gate electrode that are formed on the AlGaN layer, and edge sidewalls of the silicon layer, the buffer layer, the GaN layer, and the AlGaN layer contact an increased-resistivity region.

Abstract translation: 在硅衬底上提供高耐压GaN基晶体管。 一种氮化物半导体器件，包括：硅衬底，层叠在所述硅衬底上并具有100nm以上的膜厚度的SiO 2层; 层叠在SiO 2层上的硅层; 堆叠在所述硅层上的缓冲层; 堆叠在缓冲层上的GaN层; 堆叠在GaN层上的AlGaN层; 以及形成在AlGaN层上的源电极，漏电极和栅电极，硅层，缓冲层，GaN层和AlGaN层的边缘侧壁与增加电阻率的区域接触。

公开(公告)号：US07910464B2

公开(公告)日：2011-03-22

申请号：US12695759

申请日：2010-01-28

Applicant: Tomohiro Murata ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

Inventor： Tomohiro Murata ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L29/66871 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/8128

Abstract: A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region.

Abstract translation: 本发明的半导体器件包括：III-V族氮化物半导体层，其包括载流子行进的沟道区; 设置在III-V族氮化物半导体层中的沟道区的上部的凹部; 和由形成与半导体层形成肖特基结的导电材料构成的肖特基电极，形成在III-V族氮化物半导体层上的在凹部的凹部和周边部分上方扩散的半导体层上。 深度方向上的凹部的尺寸被设定为使得设置在凹部中的肖特基电极的一部分可以调节在沟道区域中行进的载流子的量。

公开(公告)号：US07898002B2

公开(公告)日：2011-03-01

申请号：US11890480

申请日：2007-08-07

Applicant: Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

Inventor： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC: H01L21/337 ,  H01L21/335

CPC classification number: H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/66462

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.

Abstract translation: 氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。 所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

公开(公告)号：US20100327293A1

公开(公告)日：2010-12-30

申请号：US12880704

申请日：2010-09-13

Applicant: Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

Inventor： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC: H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

Abstract translation: 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

公开(公告)号：US07859087B2

公开(公告)日：2010-12-28

申请号：US12637240

申请日：2009-12-14

Applicant: Tomohiro Murata ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Tomohiro Murata ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L23/58

CPC classification number: H01L29/7787 ,  H01L23/367 ,  H01L23/3677 ,  H01L29/2003 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

公开(公告)号：USRE41625E1

公开(公告)日：2010-09-07

申请号：US10829476

申请日：2004-04-22

Applicant: Yoshihisa Nagano ,  Yasuhiro Uemoto

Inventor： Yoshihisa Nagano ,  Yasuhiro Uemoto

IPC: H01L29/94

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

Abstract translation: 保护绝缘膜沉积在形成在半导体衬底上的第一和第二场效应晶体管上。 在保护绝缘膜上形成由电容器下电极构成的电容器，由绝缘金属氧化物膜构成的电容绝缘膜和电容器上电极。 形成在保护绝缘膜中的第一接触插塞提供电容器下电极和第一场效应晶体管的杂质扩散层之间的直接连接。 形成在保护绝缘膜中的第二接触插塞提供电容器上电极和第二场效应晶体管的杂质扩散层之间的直接连接。

公开(公告)号：US20100207164A1

公开(公告)日：2010-08-19

申请号：US12682007

申请日：2009-08-07

Applicant: Daisuke Shibata ,  Tatsuo Morita ,  Yasuhiro Uemoto

Inventor： Daisuke Shibata ,  Tatsuo Morita ,  Yasuhiro Uemoto

IPC: H01L29/772

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/41766

Abstract: A field effect transistor includes a first nitride semiconductor layer 13 and a second nitride semiconductor layer 14 having a band gap larger than that of the first nitride semiconductor layer 13 which are formed in this order in an upward direction on a conductive substrate 11, a source electrode 15 and a drain electrode 16 which are electrically connected to a two-dimensional electron gas layer 21, and a gate electrode 18. A rise voltage of a drain-substrate current is lower than a rise voltage of a drain-gate current and a rise voltage of a drain-source current.

Abstract translation: 场效应晶体管包括第一氮化物半导体层13和具有大于第一氮化物半导体层13的带隙的第二氮化物半导体层14，该第二氮化物半导体层14在导电基板11上沿向上方向依次形成，源极 与二维电子气体层21电连接的电极15和漏电极16以及栅极电极18.漏极 - 基板电流的上升电压低于漏极 - 栅极电流的上升电压，并且 漏 - 源电流的上升电压。

公开(公告)号：US20100090250A1

公开(公告)日：2010-04-15

申请号：US12637240

申请日：2009-12-14

Applicant: Tomohiro MURATA ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Tomohiro MURATA ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L29/205 ,  H01L29/772 ,  H01L29/06

CPC classification number: H01L29/7787 ,  H01L23/367 ,  H01L23/3677 ,  H01L29/2003 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

Abstract translation: 半导体器件包括：半导体层; 形成在与半导体层接触的半导体层上的至少一个电极; 以及覆盖半导体层和电极的顶表面的至少一部分的钝化膜，以保护半导体层并由多个子膜形成。 钝化膜包括由氮化铝制成的第一子膜。