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    Low-K gate spacers by fluorine implantation
    2.
    发明授权
    Low-K gate spacers by fluorine implantation 有权
    通过氟注入的低K栅间隔

    公开(公告)号：US06720213B1

    公开(公告)日：2004-04-13

    申请号：US10345344

    申请日：2003-01-15

    申请人： Jeffrey P. Gambino ,  Jack Mandelman ,  William R. Tonti

    发明人： Jeffrey P. Gambino ,  Jack Mandelman ,  William R. Tonti

    IPC分类号： H01L21338

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/4983 ,  H01L29/6656 ,  Y10S257/90

    摘要： A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.

    摘要翻译： MOSFET器件和制造具有通过氟注入产生的低K电介质氧化物栅极侧壁间隔物的MOSFET器件的方法。 本发明将氟注入到栅极氧化物侧壁间隔物中，其用于改变高级复合栅极电介质的性质，例如， 氮化的氧化物，NO和栅极侧壁电介质，使得氟的低K特性用于开发低寄生电容MOSFET。

    Trench field shield in trench isolation
    4.
    发明授权
    Trench field shield in trench isolation 失效
    沟槽隔离屏蔽沟槽

    公开(公告)号：US06420749B1

    公开(公告)日：2002-07-16

    申请号：US09602427

    申请日：2000-06-23

    申请人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl Radens ,  William R. Tonti

    发明人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl Radens ,  William R. Tonti

    IPC分类号： H01L27108

    CPC分类号： H01L21/823481 ,  H01L21/743 ,  H01L21/76232 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/10897

    摘要： A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.

    摘要翻译： 一种用于半导体器件的方法和结构，其包括：衬底，其包括沟槽，在衬底上隔离的衬底上的多个器件，沟槽内的导电侧壁间隔物，以及填充导电侧壁间隔物之间​​的沟槽的绝缘体。 第一导电侧壁间隔件电连接到所述多个器件中的第一器件，并且第二导电侧壁间隔件电连接到多个器件中的第二器件。 第一装置可以独立于第二装置而被偏置。 接触件在衬底的表面上方延伸。 第一接触件邻接第一器件和第一导电侧壁间隔物。 绝缘体将导电侧墙隔离开。 第一接触件可以在第一导体和第二导体之间等距。 导电侧壁间隔件包括场屏蔽。

    ANTI-FUSE STRUCTURE OPTIONALLY INTEGRATED WITH GUARD RING STRUCTURE
    7.
    发明申请
    ANTI-FUSE STRUCTURE OPTIONALLY INTEGRATED WITH GUARD RING STRUCTURE 审中-公开
    防腐结构选择性地与保护环结构集成

    公开(公告)号：US20080029844A1

    公开(公告)日：2008-02-07

    申请号：US11462070

    申请日：2006-08-03

    申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  William R. Tonti

    发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  William R. Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An anti-fuse structure and a related method for fabricating the anti-fuse structure include a doped well within a semiconductor substrate. A first aperture and a second aperture that expose the doped well are located within a dielectric layer located over the semiconductor substrate and the doped well. A first conductor layer is located within the first aperture and a second conductor layer is located within the second aperture. At least a first anti-fuse material layer contacts the first conductor layer. The first conductor layer and the second conductor layer may comprise doped conductor materials that upon fusing of the anti-fuse structure provide an anti-fuse diode or an anti-fuse resistor.

    摘要翻译： 用于制造抗熔丝结构的反熔丝结构和相关方法包括半导体衬底内的掺杂阱。 暴露掺杂阱的第一孔径和第二孔径位于位于半导体衬底和掺杂阱上方的电介质层内。 第一导体层位于第一孔内，第二导体层位于第二孔内。 至少第一反熔丝材料层接触第一导体层。 第一导体层和第二导体层可以包括掺杂的导体材料，其在抗熔丝结构融合时提供抗熔丝二极管或抗熔丝电阻器。

    Structure and method for dual gate oxidation for CMOS technology
    8.
    发明授权
    Structure and method for dual gate oxidation for CMOS technology 失效
    用于CMOS技术的双栅极氧化的结构和方法

    公开(公告)号：US06674134B2

    公开(公告)日：2004-01-06

    申请号：US09173430

    申请日：1998-10-15

    申请人： Wayne S. Berry ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Wayne S. Berry ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L2976

    CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/823462

    摘要： The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.

    摘要翻译： 本发明提供一种集成电路，其包括其中形成有多个器件区的衬底，所述多个器件区通过浅沟槽隔离（STI）区域彼此电隔离，并且所述多个器件区域各自具有相对的边缘邻接 其对应的STI区域; 所选择的所述器件区域具有预先选择的第一器件宽度，使得形成在其上的氧化物层与不相邻其对应的STI区的较薄的中心区域相比，沿着所述相对的边缘包括基本上较厚的周边区域; 以及选定的其它器件区域具有基本上比第一器件宽度窄的宽度的预选器件宽度，使得形成在其上的氧化物层包括沿相对边缘的周边区域，该周边区域在其中心区域上彼此邻接，从而防止形成 相应较薄的中心区域。

    Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion
    9.
    发明授权
    Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion 失效
    用于使用受控栅极耗尽的CMOS器件形成混合高压（HV / LV）晶体管的方法

    公开(公告)号：US06436749B1

    公开(公告)日：2002-08-20

    申请号：US09658655

    申请日：2000-09-08

    申请人： William R. Tonti ,  Claude L. Bertin ,  Jeffrey P. Gambino ,  Russell J. Houghton ,  Jack A. Mandelman ,  Wilbur D. Pricer

    发明人： William R. Tonti ,  Claude L. Bertin ,  Jeffrey P. Gambino ,  Russell J. Houghton ,  Jack A. Mandelman ,  Wilbur D. Pricer

    IPC分类号： H01L218238

    CPC分类号： H01L27/092 ,  H01L21/823842

    摘要： A method for forming mixed high voltage/low voltage (HV/LV) transistors for CMOS devices is disclosed. In an exemplary embodiment, depletion of the gate conductor is controlled by leaving a fixed region of the gate conductor intrinsic, or lightly doped, thus separating the heavily doped low resistivity portion of the electrode with an intrinsic region by use of a conducting dopant barrier. The barrier is conductive in nature, but acts as a well-controlled diffusion barrier, stopping the “fast” diffusion which normally takes place in polysilicon, and eliminating diffusion between the conductors. Thereby, the device performance may be precisely predicted by carefully controlling the gate conductor thickness.

    摘要翻译： 公开了一种用于形成用于CMOS器件的混合高压/低压（HV / LV）晶体管的方法。 在示例性实施例中，通过将栅极导体的固定区域固有或轻掺杂来控制栅极导体的耗尽，从而通过使用导电掺杂剂屏障将本征区域的重掺杂低电阻率部分与本征区域分离。 阻挡层本质上是导电的，但是作为良好控制的扩散屏障，停止通常在多晶硅中发生的“快速”扩散，并消除导体之间的扩散。 因此，可以通过仔细地控制栅极导体厚度来精确地预测器件性能。

    Low resistance fill for deep trench capacitor
    10.
    发明授权
    Low resistance fill for deep trench capacitor 失效
    深沟槽电容器的低电阻填充

    公开(公告)号：US06258689B1

    公开(公告)日：2001-07-10

    申请号：US09626328

    申请日：2000-07-26

    申请人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

    发明人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

    IPC分类号： H01L2120

    CPC分类号： H01L27/10861 ,  H01L29/66181

    摘要： Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.

    摘要翻译： 使用导致在沟槽的下部区域中作为节点电极的一部分的金属氮化物的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含金属氮化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元布局和/或降低的单元访问时间。 本发明的沟槽电容器特别可用作具有各种沟槽结构和设计的DRAM存储单元的组件。