公开(公告)号：US20050045888A1

公开(公告)日：2005-03-03

申请号：US10896899

申请日：2004-07-23

申请人： Tadashi Kadowaki ,  Hiroyuki Umimoto ,  Takato Handa

发明人： Tadashi Kadowaki ,  Hiroyuki Umimoto ,  Takato Handa

IPC分类号： H01L27/04 ,  H01L21/265 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/108 ,  H01L29/00 ,  H01L29/78 ,  H01L29/93 ,  H01L29/94

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device comprises varactor regions Va and transistor regions Tr. An active region for a varactor is formed with a substrate contact impurity diffusion region obtained by doping an N well region with N-type impurity at a relatively high concentration. However, any extension region (or LDD region) as in a varactor of a known semiconductor device is not formed in the active region for a varactor. On the other hand, parts of a P well region located to both sides of the polysilicon gate electrode in the transistor region Tr are formed with high-concentration source/drain regions and extension regions. Therefore, the extendable range of a depletion layer is kept wide to extend the capacitance variable range of the varactor.

摘要翻译： 半导体器件包括变容二极管区域Va和晶体管区域Tr。 通过用比较高浓度的N型杂质掺杂N阱区而得到的衬底接触杂质扩散区，形成有功变区域的有源区。 然而，在已知半导体器件的变容二极管中的任何延伸区域（或LDD区域）都不会在变容二极管的有源区域中形成。 另一方面，位于晶体管区Tr中的多晶硅栅电极两侧的P阱区的部分由高浓度源/漏区和延伸区形成。 因此，耗尽层的可扩展范围保持宽以扩大变容二极管的电容可变范围。

公开(公告)号：US20050054195A1

公开(公告)日：2005-03-10

申请号：US10900272

申请日：2004-07-28

申请人： Takato Handa ,  Hiroyuki Umimoto ,  Tetsuya Ueda

发明人： Takato Handa ,  Hiroyuki Umimoto ,  Tetsuya Ueda

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76843 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inventive semiconductor device includes: a lower interlayer dielectric film provided on a substrate; a lower interconnect made up of a lower barrier metal layer formed along a wall surface of a lower interconnect groove in the lower interlayer dielectric film, and a copper film; and an upper plug and an upper interconnect. The upper plug passes through a silicon nitride film and comes into contact with the copper film of the lower interconnect. The lower interconnect is provided with a large number of convex portions buried in concave portions of the lower interconnect groove. Thus, voids in the lower interconnect are also gettered by the convex portions. Accordingly, the concentration of voids in the contact area between the lower interconnect and the upper plug is relieved, and an increase in contact resistance is suppressed.

摘要翻译： 本发明的半导体器件包括：设置在基板上的下层间绝缘膜; 由沿下层间电介质膜的下互连槽的壁面形成的下阻挡金属层和铜膜构成的下互连件; 以及上部插头和上部互连件。 上塞通过氮化硅膜并与下互连的铜膜接触。 下部互连件设置有埋在下部互连槽的凹部中的大量凸部。 因此，下部互连件中的空隙也被凸起部分吸收。 因此，下部布线和上部插塞之间的接触区域中的空隙的浓度被释放，并且抑制了接触电阻的增加。

公开(公告)号：US07259418B2

公开(公告)日：2007-08-21

申请号：US10896899

申请日：2004-07-23

申请人： Tadashi Kadowaki ,  Hiroyuki Umimoto ,  Takato Handa

发明人： Tadashi Kadowaki ,  Hiroyuki Umimoto ,  Takato Handa

IPC分类号： H01L29/93

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device comprises varactor regions Va and transistor regions Tr. An active region for a varactor is formed with a substrate contact impurity diffusion region obtained by doping an N well region with N-type impurity at a relatively high concentration. However, any extension region (or LDD region) as in a varactor of a known semiconductor device is not formed in the active region for a varactor. On the other hand, parts of a P well region located to both sides of the polysilicon gate electrode in the transistor region Tr are formed with high-concentration source/drain regions and extension regions. Therefore, the extendable range of a depletion layer is kept wide to extend the capacitance variable range of the varactor.

摘要翻译： 半导体器件包括变容二极管区域Va和晶体管区域Tr。 通过用比较高浓度的N型杂质掺杂N阱区而得到的衬底接触杂质扩散区，形成有功变区域的有源区。 然而，在已知半导体器件的变容二极管中的任何延伸区域（或LDD区域）都不会在变容二极管的有源区域中形成。 另一方面，位于晶体管区Tr中的多晶硅栅电极两侧的P阱区的部分由高浓度源/漏区和延伸区形成。 因此，耗尽层的可扩展范围保持宽以扩大变容二极管的电容可变范围。

公开(公告)号：US07265450B2

公开(公告)日：2007-09-04

申请号：US10900272

申请日：2004-07-28

申请人： Takato Handa ,  Hiroyuki Umimoto ,  Tetsuya Ueda

发明人： Takato Handa ,  Hiroyuki Umimoto ,  Tetsuya Ueda

IPC分类号： H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inventive semiconductor device includes: a lower interlayer dielectric film provided on a substrate; a lower interconnect made up of a lower barrier metal layer formed along a wall surface of a lower interconnect groove in the lower interlayer dielectric film, and a copper film; and an upper plug and an upper interconnect. The upper plug passes through a silicon nitride film and comes into contact with the copper film of the lower interconnect. The lower interconnect is provided with a large number of convex portions buried in concave portions of the lower interconnect groove. Thus, voids in the lower interconnect are also gettered by the convex portions. Accordingly, the concentration of voids in the contact area between the lower interconnect and the upper plug is relieved, and an increase in contact resistance is suppressed.

摘要翻译： 本发明的半导体器件包括：设置在基板上的下层间绝缘膜; 由沿下层间电介质膜的下互连槽的壁面形成的下阻挡金属层和铜膜构成的下互连件; 以及上部插头和上部互连件。 上塞通过氮化硅膜并与下互连的铜膜接触。 下部互连件设置有埋在下部互连槽的凹部中的大量凸部。 因此，下部互连件中的空隙也被凸起部分吸收。 因此，下部布线和上部插塞之间的接触区域中的空隙的浓度被释放，并且抑制了接触电阻的增加。

公开(公告)号：US06821830B2

公开(公告)日：2004-11-23

申请号：US10647284

申请日：2003-08-26

申请人： Takato Handa ,  Hiroyuki Umimoto

发明人： Takato Handa ,  Hiroyuki Umimoto

IPC分类号： H01L21338

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7835

摘要： A hard mask 21a which has an opening for exposing a p-type region 2 defined in a silicon substrate 1 and is made of, for example, a BPSG film is formed. Then, the hard mask 21a is subjected to isotropic etching using argon gas, to have its edge rounded off, thereby forming an implantation hard mask 21 having a tapered edge. Subsequently, large-angle-tilt ion implantation of an n-type impurity is performed using the implantation hard mask 21 as a mask, thereby forming an n− layer 13 having an LDD structure. Thereafter, the implantation hard mask 11 is removed. In this manner, it is possible to perform large-angle-tilt ion implantation using an implantation mask thinner than a conventional implantation mask.

摘要翻译： 形成具有用于露出硅基板1中限定的并由例如BPSG膜制成的p型区域2的开口的硬掩模21a。 然后，使用氩气对硬掩模21a进行各向同性蚀刻，使其边缘倒圆，从而形成具有锥形边缘的注入硬掩模21。 随后，使用注入硬掩模21作为掩模进行n型杂质的大角度倾斜离子注入，从而形成具有LDD结构的n层13。 此后，移除注入硬掩模11。 以这种方式，可以使用比常规植入掩模更薄的注入掩模进行大角度倾斜离子注入。

公开(公告)号：US07301208B2

公开(公告)日：2007-11-27

申请号：US11118389

申请日：2005-05-02

申请人： Takato Handa ,  Kazumi Kurimoto

发明人： Takato Handa ,  Kazumi Kurimoto

IPC分类号： H01L29/76 ,  H01L31/062 ,  H01L29/94

CPC分类号： H01L29/0847 ,  H01L29/105 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A first doped layer of a conductivity type opposite to that of source/drain regions is formed in a semiconductor substrate under a gate electrode. A second doped layer of the conductivity type opposite to that of the source/drain regions is formed in the semiconductor substrate below the first doped layer. The first doped layer has a first peak in dopant concentration distribution in the depth direction. The first peak is located at a position shallower than the junction depth of the source/drain regions. The second doped layer has a second peak in dopant concentration distribution in the depth direction. The second peak is located at a position deeper than the first peak and shallower than the junction depth of the source/drain regions. The dopant concentration at the first peak is higher than that at the second peak.

摘要翻译： 在栅电极下的半导体衬底中形成与源极/漏极区相反的导电类型的第一掺杂层。 在第一掺杂层下方的半导体衬底中形成与源极/漏极区相反的导电类型的第二掺杂层。 第一掺杂层在深度方向上具有掺杂剂浓度分布中的第一峰。 第一峰位于比源/漏区的结深更浅的位置。 第二掺杂层在深度方向上具有掺杂剂浓度分布中的第二峰。 第二峰位于比第一峰更深的位置，比源极/漏极区的结深更浅。 第一峰处的掺杂浓度高于第二峰处的掺杂浓度。

公开(公告)号：US20060027865A1

公开(公告)日：2006-02-09

申请号：US11118389

申请日：2005-05-02

申请人： Takato Handa ,  Kazumi Kurimoto

发明人： Takato Handa ,  Kazumi Kurimoto

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/105 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A first doped layer of a conductivity type opposite to that of source/drain regions is formed in a semiconductor substrate under a gate electrode. A second doped layer of the conductivity type opposite to that of the source/drain regions is formed in the semiconductor substrate below the first doped layer. The first doped layer has a first peak in dopant concentration distribution in the depth direction. The first peak is located at a position shallower than the junction depth of the source/drain regions. The second doped layer has a second peak in dopant concentration distribution in the depth direction. The second peak is located at a position deeper than the first peak and shallower than the junction depth of the source/drain regions. The dopant concentration at the first peak is higher than that at the second peak.

摘要翻译： 在栅电极下的半导体衬底中形成与源极/漏极区相反的导电类型的第一掺杂层。 在第一掺杂层下方的半导体衬底中形成与源极/漏极区相反的导电类型的第二掺杂层。 第一掺杂层在深度方向上具有掺杂剂浓度分布中的第一峰。 第一峰位于比源/漏区的结深更浅的位置。 第二掺杂层在深度方向上具有掺杂剂浓度分布中的第二峰。 第二峰位于比第一峰更深的位置，比源极/漏极区的结深更浅。 第一峰处的掺杂浓度高于第二峰处的掺杂浓度。