公开(公告)号：US06620716B2

公开(公告)日：2003-09-16

申请号：US10114453

申请日：2002-04-03

申请人： Kozo Makiyama ,  Katsumi Ogiri

发明人： Kozo Makiyama ,  Katsumi Ogiri

IPC分类号： H01L21338

CPC分类号： H01L29/66462 ,  H01L21/28114 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/42376

摘要： A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding like an overhang, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.

摘要翻译： 制造半导体器件的方法包括通过执行多个显影步骤形成具有多层结构的抗蚀剂图案，所述抗蚀剂图案包括对应于栅电极的精细栅极部分的第一开口和位于所述栅电极上的第二开口 所述第二开口对应于比所述细门部分宽的横截面部分，并且具有如悬垂突出的横截面，其中所述过门部分顶端处的所述第二开口的每个角度大于 90度; 以及通过在抗蚀剂图案上沉积电极材料来形成设置有精细栅极部分和栅极极化部分的栅电极。

公开(公告)号：US06784036B2

公开(公告)日：2004-08-31

申请号：US10456493

申请日：2003-06-09

申请人： Kozo Makiyama ,  Katsumi Ogiri

发明人： Kozo Makiyama ,  Katsumi Ogiri

IPC分类号： H01L21338

CPC分类号： H01L29/66462 ,  H01L21/28114 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/42376

摘要： A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding over an undercut in an underlying layer, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.

摘要翻译： 制造半导体器件的方法包括通过执行多个显影步骤形成具有多层结构的抗蚀剂图案，所述抗蚀剂图案包括对应于栅电极的精细栅极部分的第一开口和位于所述栅电极上的第二开口 第一开口，第二开口对应于比精细门部分更宽的横截面部分，并且具有在下层中的底切上突出的横截面，其中在过门顶端处的第二开口的每个角度 截面超过90度; 以及通过在抗蚀剂图案上沉积电极材料来形成设置有精细栅极部分和栅极极化部分的栅电极。

公开(公告)号：US06509252B1

公开(公告)日：2003-01-21

申请号：US10114452

申请日：2002-04-03

申请人： Kozo Makiyama ,  Katsumi Ogiri

发明人： Kozo Makiyama ,  Katsumi Ogiri

IPC分类号： H01L2120

CPC分类号： H01L29/66848 ,  H01L21/0273

摘要： A method of manufacturing a semiconductor device includes an exposing step of transferring a support pattern onto an non-exposed area of a resist layer so that an opening for forming a support is formed in a thick part of the resist layer. The support is formed simultaneously with a gate electrode in a body using the resist layer having the opening. The gate electrode on a mesa extending into the outside of the mesa is supported by both a mesa layer and the support.

摘要翻译： 制造半导体器件的方法包括将支持图案转印到抗蚀剂层的未曝光区域上的曝光步骤，使得在抗蚀剂层的厚部分中形成用于形成支撑体的开口。 支撑体与使用具有开口的抗蚀剂层的主体中的栅电极同时形成。 延伸到台面外部的台面上的栅电极由台面层和支撑体两者支撑。