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    PHYSICALLY UNCLONABLE FUNCTION PRODUCED USING OTP MEMORY
    1.
    发明申请
    PHYSICALLY UNCLONABLE FUNCTION PRODUCED USING OTP MEMORY 有权

    公开(公告)号：US20220385486A1

    公开(公告)日：2022-12-01

    申请号：US17828018

    申请日：2022-05-30

    Applicant: Attopsemi Technology Co., LTD

    Inventor： Shine C. Chung

    IPC: H04L9/32 ,  G11C7/24 ,  G11C17/16 ,  G11C17/18

    Abstract: An electronic device and method of generating a Physically Unclonable Function (“PUF”) value is disclosed. An OTP memory with a plurality of OTP cells that can be reliably and deterministically programmed with a minimum and a maximum program voltage being selected for pre-conditioning. All OTP cells can be programmed at least once around the minimum program voltage to hide the program status. Data to be programmed into the OTP can be a fixed, time-varying voltage or data from an entropy source. The programmed OTP data can be masked for weak bits and further randomized to generate PUF output by compressing a bit stream into a single bit, e.g., single parity bit. The PUF output can be through a hash function and/or to generate keys.

    Fully testible OTP memory
    2.
    发明授权
    Fully testible OTP memory 有权

    公开(公告)号：US10923204B2

    公开(公告)日：2021-02-16

    申请号：US16273023

    申请日：2019-02-11

    Applicant: Attopsemi Technology Co., LTD

    Inventor： Shine C. Chung

    IPC: G11C17/16 ,  G11C29/02 ,  G11C17/18 ,  G11C29/50 ,  G11C29/06

    Abstract: A method of testing an OTP memory is disclosed. An OTP program mechanism that uses heat accelerated electromigration can be fully tested. In one embodiment, an OTP cell's programmability can be tested if an initial OTP element resistance is less than a predetermined resistance, as such insures that sufficient heat can be generated to be programmable. A non-destructive program state, or fake reading 1, can be created by low-voltage programming a cell while reading the same cell at the same time. Accordingly, alternative 0s and 1s patterns can be generated to fully test every functional block of an OTP memory.

    PROGRAMMABLE RESISTANCE MEMORY ON THIN FILM TRANSISTOR TECHNOLOGY
    3.
    发明申请
    PROGRAMMABLE RESISTANCE MEMORY ON THIN FILM TRANSISTOR TECHNOLOGY 审中-公开

    公开(公告)号：US20200219574A1

    公开(公告)日：2020-07-09

    申请号：US16803992

    申请日：2020-02-27

    Applicant: Attopsemi Technology, Co., LTD

    Inventor： Shine C. Chung

    IPC: G11C17/16 ,  G11C17/18 ,  G11C29/02

    Abstract: Programmable resistive memory can be fabricated with a non-single-crystalline silicon formed on a flexible substrate. The non-single-crystalline silicon can be amorphous silicon, low-temperature polysilicon (LTPS), organic semiconductor, or metal oxide semiconductor. The flexible substrate can be glass, plastics, paper, metal, paper, or any kinds of flexible film. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a silicon, polysilicon, organic or metal oxide electrode. The selector in a programmable resistive memory can be a MOS or diode with top gate, bottom gate, inverted, staggered, or coplanar structures.

    One-Time Programmable Device with Integrated Heat Sink
    4.
    发明申请
    One-Time Programmable Device with Integrated Heat Sink 审中-公开
    具有集成散热器的一次性可编程器件

    公开(公告)号：US20170047126A1

    公开(公告)日：2017-02-16

    申请号：US15297922

    申请日：2016-10-19

    Applicant: Attopsemi Technology Co., LTD

    Inventor： Shine C. Chung

    IPC: G11C17/06 ,  H01L27/112 ,  G11C17/16

    CPC classification number: G11C17/06 ,  G11C7/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C17/02 ,  G11C17/16 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0054 ,  G11C2213/72 ,  G11C2213/74 ,  H01L23/5256 ,  H01L27/1021 ,  H01L27/11206 ,  H01L29/0649 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/732 ,  H01L29/861 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, metal-0, thermally isolated active region, CMOS gate, or combination thereof.

    Abstract translation: 以标准CMOS逻辑工艺制造的结二极管可用作具有至少一个散热器或加热器的程序选择器，以辅助一次性可编程（OTP）器件的编程，例如电熔丝，接触/通路保险丝，接触/ 保险丝或栅极氧化物击穿反熔丝等。散热器可以是至少一个薄氧化物区域，扩展OTP元件区域或耦合到OTP元件的其它导体以辅助编程。 加热器可以是至少一个高电阻区域，例如未硅化的多晶硅，非硅化的有源区，接触，通孔，或串联连接或互连以产生热量以辅助编程。 OTP器件具有耦合到存储器单元中的至少一个二极管的至少一个OTP元件。 二极管可以由CMOS N阱中的P +和N +有源区域或作为二极管的P和N端子的隔离有源区域构成。 可以通过虚拟MOS栅极，SBL或STI / LOCOS隔离来提供单元中或单元之间的二极管的P +与N +有源区之间的隔离。 OTP元件可以是多晶硅，硅化多晶硅，硅化物，多金属，金属，金属合金，局部互连，金属-O，热隔离有源区，CMOS栅极或其组合。

    One-time programmable memories with ultra-low power read operation and novel sensing scheme
    5.
    发明授权
    One-time programmable memories with ultra-low power read operation and novel sensing scheme 有权

    公开(公告)号：US11615859B2

    公开(公告)日：2023-03-28

    申请号：US17373733

    申请日：2021-07-12

    Applicant: Attopsemi Technology Co., LTD

    Inventor： Shine C. Chung

    IPC: G11C17/18 ,  G11C17/16

    Abstract: An OTP with ultra-low power read can be programmed with a minimum and a maximum program voltage. When programming within the range, the post-program OTP to pre-program resistance ratio can be larger than N, where N>50, so that more sensing techniques, such as single-end sensing, can be used to reduce read current. At least one of the OTP cells can be coupled to a common bitline, which can be further coupled to a first supply voltage lines via a plurality of datalines. The resistance in the at least one OTP cell can be evaluated by strobing at least one comparator output of the discharging bitline/dataline.

    ONE-TIME PROGRAMMABLE MEMORY DEVICES USING FinFET TECHNOLOGY
    10.
    发明申请
    ONE-TIME PROGRAMMABLE MEMORY DEVICES USING FinFET TECHNOLOGY 审中-公开
    一次性可编程存储器件使用FinFET技术

    公开(公告)号：US20170062071A1

    公开(公告)日：2017-03-02

    申请号：US15270287

    申请日：2016-09-20

    Applicant: Attopsemi Technology Co., Ltd

    Inventor： Shine C. Chung

    IPC: G11C17/18 ,  H01L27/112 ,  G11C17/06 ,  G11C17/16 ,  G11C13/00

    CPC classification number: G11C17/18 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C17/06 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0054 ,  G11C2213/72 ,  G11C2213/74 ,  H01L23/5256 ,  H01L27/1021 ,  H01L27/11206 ,  H01L29/0649 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/732 ,  H01L29/785 ,  H01L29/861 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An OTP (One-Time Programmable) memory including OTP memory cells that utilize OTP elements fabricated in CMOS FinFET processes. The OTP memory cell can also include at least one selector built upon at least one fin structure that has at least one CMOS gate to divide the fin structure into at least a first and a second active region. The selector can be implemented as a MOS device, dummy-gate diode, or Schottky diode as selector such as by using different types of source/drain implants. The OTP element that can be implemented as polysilicon, silicided polysilicon, CMOS metal gate, any layers of metal as interconnect, or active region. In one embodiment, the OTP element can be a fin structure and can be built upon the same fin structure as the at least one of the selector. By using different source/drain implant schemes on the two active regions, the selector can be turned on as MOS device, MOS device and/or diode, dummy-gate diode, or Schottky diode.

    Abstract translation: 一个OTP（一次可编程）存储器，包括使用在CMOS FinFET工艺中制造的OTP元件的OTP存储器单元。 OTP存储器单元还可以包括至少一个选择器，其构建在至少一个鳍结构上，该至少一个鳍结构具有至少一个CMOS栅极，以将鳍结构分成至少第一和第二有源区。 选择器可以被实现为MOS器件，伪栅极二极管或肖特基二极管作为选择器，例如通过使用不同类型的源/漏植入物。 可以实现为多晶硅，硅化多晶硅，CMOS金属栅极，任何金属层作为互连的OTP元件或有源区。 在一个实施例中，OTP元件可以是翅片结构，并且可以构建为与选择器中的至少一个相同的鳍结构。 通过在两个有源区域上使用不同的源极/漏极注入方案，选择器可以作为MOS器件，MOS器件和/或二极管，伪栅极二极管或肖特基二极管导通。

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