公开(公告)号：US20230017383A1

公开(公告)日：2023-01-19

申请号：US17375654

申请日：2021-07-14

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Joung Joo LEE ,  Komal GARDE ,  Kishor Kumar KALATHIPARAMBIL ,  Xianmin TANG ,  Xiangjin XIE ,  Rui LI

IPC: H01L21/768 ,  H01L21/285 ,  C23C14/34

Abstract: Methods and apparatus for processing a substrate are provided. For example, a method includes sputtering a material from a target in a PVD chamber to form a material layer on a layer comprising a feature of the substrate, the feature having an opening width defined by a first sidewall and a second sidewall, the material layer having a greater lateral thickness at the top surface of the layer than a thickness on the first sidewall or the second sidewall within the feature, depositing additional material on the layer by biasing the layer with an RF bias at a low power, etching the material layer from the layer by biasing the layer with an RF bias at a high-power, and repeatedly alternating between the low power and the high-power at a predetermined frequency.

公开(公告)号：US20170092502A1

公开(公告)日：2017-03-30

申请号：US15240410

申请日：2016-08-18

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Ellie Y. YIEH ,  Mehul B. NAIK ,  Srinivas D. NEMANI

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/28518 ,  C23C16/42 ,  C23C16/4418 ,  C23C16/511 ,  C23C16/56 ,  H01L21/02532 ,  H01L21/28556 ,  H01L21/324 ,  H01L21/76864 ,  H01L21/76885 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53271

Abstract: Implementations described herein generally relate to methods of selective deposition of metal silicides. More specifically, implementations described herein generally relate to methods of forming nickel silicide nanowires for semiconductor applications. In one implementation, a method of processing a substrate is provided. The method comprises forming a silicon-containing layer on a surface of a substrate, forming a metal-containing layer comprising a transition metal on the silicon-containing layer, forming a confinement layer on exposed surfaces of the metal-containing layer and annealing the substrate at a temperature of less than 400 degrees Celsius to form a metal silicide layer from the silicon-containing layer and the metal-containing layer, wherein the confinement layer inhibits formation of metal-rich metal silicide phases.

公开(公告)号：US20160049305A1

公开(公告)日：2016-02-18

申请号：US14799374

申请日：2015-07-14

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Bok Hoen KIM ,  Deenesh PADHI ,  Li Yan MIAO ,  Pramit MANNA ,  Christopher Dennis BENCHER ,  Mehul B. NAIK ,  Huixiong DAI ,  Christopher S. NGAI ,  Daniel Lee DIEHL

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/3088 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144

Abstract: Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded.

Abstract translation: 本公开的实施例通常提供在与上覆光致抗蚀剂层光学匹配的硬掩模中形成减小尺寸图案的方法。 该方法通常包括在低于光致抗蚀剂的分解温度的温度下，在图案化的光致抗蚀剂和下面的硬掩模的场区域，侧壁和底部上施加尺寸收缩的保形碳层。 本文的方法和实施例还涉及通过蚀刻工艺从图案化的光致抗蚀剂和硬掩模的底部部分去除保形碳层，以暴露硬掩模，在底部蚀刻暴露的硬掩模基板，随后同时去除 保形碳层，光致抗蚀剂等碳质成分。 因此产生了用于进一步模式转移的尺寸减小特征的硬掩模。

公开(公告)号：US20190311908A1

公开(公告)日：2019-10-10

申请号：US16366539

申请日：2019-03-27

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Maximillian CLEMONS ,  Mei-Yee SHEK ,  Minrui YU ,  Bencherki MEBARKI ,  Mehul B. NAIK ,  Chentsau YING ,  Srinivas D. NEMANI

IPC: H01L21/285 ,  H01L29/45

Abstract: Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.

公开(公告)号：US20170278709A1

公开(公告)日：2017-09-28

申请号：US15602862

申请日：2017-05-23

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Pramit MANNA ,  Li Yan MIAO ,  Deenesh PADHI ,  Bok Hoen KIM ,  Christopher Dennis BENCHER

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/0337 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0273 ,  H01L21/31058 ,  H01L21/31138 ,  H01L2221/00

Abstract: Embodiments of the disclosure relate to deposition of a conformal organic material over a feature formed in a photoresist or a hardmask, to decrease the critical dimensions and line edge roughness. In various embodiments, an ultra-conformal carbon-based material is deposited over features formed in a high-resolution photoresist. The conformal organic layer formed over the photoresist thus reduces both the critical dimensions and the line edge roughness of the features.

公开(公告)号：US20160204029A1

公开(公告)日：2016-07-14

申请号：US14975028

申请日：2015-12-18

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Annamalai LAKSHMANAN ,  Kaushal K. SINGH ,  Paul F. MA ,  Mehul B. NAIK ,  Andrew COCKBURN ,  Ludovic GODET

IPC: H01L21/768 ,  H01L21/285

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide stack comprising as plurality of metal silicide layers on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide stack in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer.

Abstract translation: 提供了用于形成用于半导体应用的后端互连结构的纳米线的金属硅化物的方法和装置。 在一个实施例中，该方法包括通过化学气相沉积工艺或物理气相沉积工艺在衬底上形成包含多个金属硅化物层的金属硅化物堆叠，对处理室中的金属硅化物堆进行热处理，施加微波功率 在处理室中，同时热处理金属硅化物层; 并且在热处理金属硅化物层的同时保持低于400摄氏度的衬底温度。

公开(公告)号：US20250157790A1

公开(公告)日：2025-05-15

申请号：US18926504

申请日：2024-10-25

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Sang-Heum KIM ,  Joung Joo LEE

IPC: H01J37/32 ,  C23C14/34 ,  C23C14/35

Abstract: Embodiments described herein provide an apparatus and method for fabricating semiconductor devices with improved process control and performance. The apparatus includes a processing chamber with first and second RF coil assemblies generating primary and secondary plasmas in distinct regions, along with first and second electromagnet assemblies for independent magnetic field control. A removable biasable flux optimizer is disposed in the apparatus to modulate plasma distribution and directionality. The method involves a three-step sequence comprising Inductive coupled plasma (IMP) low energy deposition, deposition for enhanced step coverage, and etching for overhang removal. The ICP deposition utilizes primary and secondary plasmas generated by the RF coil assemblies, with intensified collisions achieved through chamber pressure increase. Additionally, a simultaneous deposition and etching process can be employed, with optional additional etching steps for improved overhang removal.

公开(公告)号：US20250132146A1

公开(公告)日：2025-04-24

申请号：US18382961

申请日：2023-10-23

Applicant: Applied Materials, Inc.

Inventor： Mohammad Mahdi TAVAKOLI ,  Chandan DAS ,  Bencherki MEBARKI ,  Joung Joo LEE ,  Jiecong TANG ,  Avgerinos V. GELATOS

IPC: H01L21/02 ,  H01L21/3213

Abstract: A method of capping a metal layer includes performing a conversion process to reduce a metal oxide layer formed on a top surface of the metal layer and form a metal sulfide layer on the top surface of the metal layer, exposing the top surface of the metal layer to an oxidizing environment, and performing a removal process to remove the metal sulfide layer.

公开(公告)号：US20170358490A1

公开(公告)日：2017-12-14

申请号：US15332737

申请日：2016-10-24

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Sean KANG ,  Keith Tatseun WONG ,  He REN ,  Mehul B. NAIK ,  Ellie Y. YIEH ,  Srinivas D. NEMANI

IPC: H01L21/768

CPC classification number: H01L21/76882 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53257

Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.

公开(公告)号：US20170294348A1

公开(公告)日：2017-10-12

申请号：US15453675

申请日：2017-03-08

Applicant: APPLIED MATERIALS, INC.

Inventor： Bencherki MEBARKI ,  Srinivas D. NEMANI ,  Mehul NAIK

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76834 ,  H01L21/76883

Abstract: A method of processing a substrate includes: depositing an etch stop layer atop a first dielectric layer; forming a feature in the etch stop layer and the first dielectric layer; depositing a first metal layer to fill the feature; etching the first metal layer to form a recess; depositing a second dielectric layer to fill the recess wherein the second dielectric layer is a low-k material suitable as a metal and oxygen diffusion barrier; forming a patterned mask layer atop the substrate to expose a portion of the second dielectric layer and the etch stop layer; etching the exposed portion of the second dielectric layer to a top surface of the first metal layer to form a via in the second dielectric layer; and depositing a second metal layer atop the substrate, wherein the second metal layer is connected to the first metal layer by the via.