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公开(公告)号：US08686388B2
公开(公告)日：2014-04-01
申请号：US13547376
申请日：2012-07-12
Applicant: Andreas Roelofs , Markus Siegert , Venugopalan Vaithyanathan , Wei Tian , Yongchul Ahn , Muralikrishnan Balakrishnan , Olle Heinonen
Inventor： Andreas Roelofs , Markus Siegert , Venugopalan Vaithyanathan , Wei Tian , Yongchul Ahn , Muralikrishnan Balakrishnan , Olle Heinonen
IPC: H01L29/02
CPC classification number: G11C13/0007 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/77 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1608
Abstract: A resistive sense memory cell includes a layer of crystalline praseodymium calcium manganese oxide and a layer of amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack. A first and second electrode are separated by the resistive sense memory stack. The resistive sense memory cell can further include an oxygen diffusion barrier layer separating the layer of crystalline praseodymium calcium manganese oxide from the layer of amorphous praseodymium calcium manganese oxide a layer. Methods include depositing an amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack.
Abstract translation: 电阻式感测存储单元包括一层结晶的镨钙锰氧化物和一层无定形的镨钙锰氧化物，其设置在形成电阻式感测存储堆的结晶镨钙锰氧化物层上。 第一和第二电极由电阻式感测存储器堆分隔开。 电阻式感测存储单元还可以包括从无定形镨钙锰氧化物层的层分离结晶镨钙锰氧化物层的氧扩散阻挡层。 方法包括沉积形成电阻式感测存储器叠层的结晶镨钙锰氧化物层上的无定形镨钙锰氧化物。
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公开(公告)号：US08309945B2
公开(公告)日：2012-11-13
申请号：US13396731
申请日：2012-02-15
Applicant: Wei Tian , Dexin Wang , Venugopalan Vaithyanathan , Yang Dong , Muralikrishnan Balakrishnan , Ivan Petrov Ivanov , Ming Sun , Dimitar Velikov Dimitrov
Inventor： Wei Tian , Dexin Wang , Venugopalan Vaithyanathan , Yang Dong , Muralikrishnan Balakrishnan , Ivan Petrov Ivanov , Ming Sun , Dimitar Velikov Dimitrov
IPC: H01L29/02
CPC classification number: B82Y10/00 , G11C13/0011 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/16
Abstract: Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.
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公开(公告)号：US08288749B2
公开(公告)日：2012-10-16
申请号：US13445351
申请日：2012-04-12
Applicant: Young Pil Kim , Nurul Amin , Dadi Setiadi , Venugopalan Vaithyanathan , Wei Tian , Insik Jin
Inventor： Young Pil Kim , Nurul Amin , Dadi Setiadi , Venugopalan Vaithyanathan , Wei Tian , Insik Jin
CPC classification number: H01L27/0814 , G11C11/161 , G11C11/1659 , G11C13/0002 , H01L21/84 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/11507 , H01L27/1203 , H01L27/224 , H01L27/2409 , H01L29/66143 , H01L29/66212 , H01L29/872 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/143 , H01L45/146 , H01L45/147
Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.
Abstract translation: 一种开关元件，包括第一半导体层，所述第一半导体层具有第一部分和第二部分; 第二半导体层，所述第二半导体层具有第一部分和第二部分; 设置在所述第一半导体层和所述第二半导体层之间的绝缘层; 与所述第一半导体层的所述第一部分接触的第一金属触点，形成第一结，并与所述第二半导体层的所述第一部分接触形成第二结; 第二金属触点与第一半导体层的第二部分接触形成第三结，并与第二半导体层的第二部分接触形成第四结，其中第一结和第四结是肖特基接触， 第二结和第三结是欧姆接触。
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公开(公告)号：US08248836B2
公开(公告)日：2012-08-21
申请号：US12501751
申请日：2009-07-13
Applicant: Insik Jin , YoungPil Kim , Ming Sun , Chulmin Jung , Venugopalan Vaithyanathan , Nurul Amin , Wei Tian , Yong Lu
Inventor： Insik Jin , YoungPil Kim , Ming Sun , Chulmin Jung , Venugopalan Vaithyanathan , Nurul Amin , Wei Tian , Yong Lu
CPC classification number: G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/76
Abstract: A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element.
Abstract translation: 一种非易失性存储单元及其使用方法。 在一些实施例中，独立可编程电阻感测存储器（RSM）元件与可编程金属化单元（PMC）开关元件串联连接。 在操作中，当开关元件被编程为第一电阻状态时，没有电流通过RSM元件，并且当第二电阻状态被编程到RSM元件时，电流通过RSM元件。
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公开(公告)号：US08203865B2
公开(公告)日：2012-06-19
申请号：US13087087
申请日：2011-04-14
Applicant: Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
Inventor： Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
IPC: G11C11/00
CPC classification number: G11C11/16 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/51 , G11C2213/76 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/1246
Abstract: A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.
Abstract translation: 公开了一种包括非欧姆选择层的非易失性存储单元和相关联的方法。 根据一些实施例，非易失性存储器单元由耦合到非欧姆选择层的电阻感测元件（RSE）组成。 响应于大于或等于预定阈值的电流，选择层被配置为从第一电阻状态转变到第二电阻状态。
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Patent Agency Ranking
6.发明授权公开(公告)号：US08022547B2
公开(公告)日：2011-09-20
申请号：US12272871
申请日：2008-11-18
Applicant: Venugopalan Vaithyanathan , Wei Tian , Insik Jin
Inventor： Venugopalan Vaithyanathan , Wei Tian , Insik Jin
CPC classification number: H01L45/1233 , H01L27/2463 , H01L27/2472 , H01L45/085 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1641 , H01L45/1675
Abstract: A non-volatile memory cell that includes a first electrode; a second electrode; and an electrical contact region that electrically connects the first electrode and the second electrode, the electrical contact region has a end portion and a continuous side portion, and together, the end portion and the continuous side portion form an open cavity, wherein the memory cell has a high resistance state and a low resistance state that can be switched by applying a voltage across the first electrode and the second electrode.
Abstract translation: 一种包括第一电极的非易失性存储单元; 第二电极; 以及电接触区域，其电连接所述第一电极和所述第二电极，所述电接触区域具有端部和连续侧部，并且所述端部和所述连续侧部一起形成开放空腔，其中所述存储单元 具有可以通过在第一电极和第二电极两端施加电压来切换的高电阻状态和低电阻状态。
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公开(公告)号：US07936585B2
公开(公告)日：2011-05-03
申请号：US12502222
申请日：2009-07-13
Applicant: Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
Inventor： Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
IPC: G11C11/00
CPC classification number: G11C11/16 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/51 , G11C2213/76 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/1246
Abstract: A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.
Abstract translation: 公开了一种包括非欧姆选择层的非易失性存储单元和相关联的方法。 根据一些实施例，非易失性存储器单元由耦合到非欧姆选择层的电阻感测元件（RSE）组成。 响应于大于或等于预定阈值的电流，选择层被配置为从第一电阻状态转变到第二电阻状态。
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公开(公告)号：US20110007545A1
公开(公告)日：2011-01-13
申请号：US12501751
申请日：2009-07-13
Applicant: Insik Jin , YoungPil Kim , Ming Sun , Chulmin Jung , Venugopalan Vaithyanathan , Nurul Amin , Wei Tian , Yong Lu
Inventor： Insik Jin , YoungPil Kim , Ming Sun , Chulmin Jung , Venugopalan Vaithyanathan , Nurul Amin , Wei Tian , Yong Lu
CPC classification number: G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/76
Abstract: A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element.
Abstract translation: 一种非易失性存储单元及其使用方法。 在一些实施例中，独立可编程电阻感测存储器（RSM）元件与可编程金属化单元（PMC）开关元件串联连接。 在操作中，当开关元件被编程为第一电阻状态时，没有电流通过RSM元件，并且当第二电阻状态被编程到RSM元件时，电流通过RSM元件。
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9.发明申请公开(公告)号：US20100110764A1
公开(公告)日：2010-05-06
申请号：US12497767
申请日：2009-07-06
Applicant: Ming Sun , Nurul Amin , Insik Jin , Young Pil Kim , Chulmin Jung , Venugopalan Vaithyanathan , Wei Tian , Hai Li
Inventor： Ming Sun , Nurul Amin , Insik Jin , Young Pil Kim , Chulmin Jung , Venugopalan Vaithyanathan , Wei Tian , Hai Li
CPC classification number: H01L45/1233 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C13/0011 , G11C13/003 , G11C2213/74 , G11C2213/76 , H01L27/2463 , H01L45/085 , H01L45/1266 , H01L45/14 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625 , H01L45/1675
Abstract: An electronic device that includes a first programmable metallization cell (PMC) that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode; and a second PMC that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode, wherein the first and second PMCs are electrically connected in anti-parallel.
Abstract translation: 一种电子设备，包括：包括有源电极的第一可编程金属化单元（PMC）; 惰性电极; 以及设置在所述有源电极和所述惰性电极之间的固体电解质层; 和包括有源电极的第二PMC; 惰性电极; 以及设置在所述有源电极和所述惰性电极之间的固体电解质层，其中所述第一和第二PMC以反平行电连接。
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公开(公告)号：US20120199936A1
公开(公告)日：2012-08-09
申请号：US13445351
申请日：2012-04-12
Applicant: Young Pil Kim , Nurul Amin , Dadi Setiadi , Venugopalan Vaithyanathan , Wei Tian , Insik Jin
Inventor： Young Pil Kim , Nurul Amin , Dadi Setiadi , Venugopalan Vaithyanathan , Wei Tian , Insik Jin
IPC: H01L29/868
CPC classification number: H01L27/0814 , G11C11/161 , G11C11/1659 , G11C13/0002 , H01L21/84 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/11507 , H01L27/1203 , H01L27/224 , H01L27/2409 , H01L29/66143 , H01L29/66212 , H01L29/872 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/143 , H01L45/146 , H01L45/147
Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.
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